Assembly and reliability of a wafer-level CSP; an experiment reveals that wafer-level devices can be assembled in high yield using standard surface-mount practices.Chip-scale package (CSP (1) (Certified Systems Professional) An earlier award for successful completion of an ICCP examination in systems development. See ICCP. (2) (Commerce Service P ) technology continues to push the limits of miniaturization min·i·a·tur·ize tr.v. min·i·a·tur·ized, min·i·a·tur·iz·ing, min·i·a·tur·iz·es To plan or make on a greatly reduced scale. min on both the package and printed circuit board (PCB PCB: see polychlorinated biphenyl. PCB in full polychlorinated biphenyl Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound. ) level. Wafer-level CSPs are individual silicon chips that contain a thin film redistribution layer to route the devices to standard surface-mount pitches. The packages are small, light and available in fine-pitch formats with I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output counts ranging from 4 to over 200. [TEXT NOT REPRODUCIBLE IN ASCII ASCII or American Standard Code for Information Interchange, a set of codes used to represent letters, numbers, a few symbols, and control characters. Originally designed for teletype operations, it has found wide application in computers. ] The fine-pitch nature of the wafer-level CSP often requires that the PCB routing incorporate via technology to fully exploit the functionality of the device. Although dog bone via structures are preferred, the density of the routing may require via-in-pad technology to accommodate the wafer-level package. The long-term reliability of wafer-level devices is a concern that must be addressed. Direct chip attach, or flip chip A chip packaging technique in which the active area of the chip is "flipped over" facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done assembly, is a proven technology that is widely used. Wafer-level devices are, more or less, large flip chips. However, flip chips rely on an underfill to improve the mechanical and thermal fatigue resistance of the package. If a wafer-level CSP is to be used as a drop-in replacement for a traditional CSP, an underfill material cannot be used. This article discusses the processes used to assemble a 46 I/O, 0.75 mm pitch wafer-level device on conventional PCB pads and on via-in-pad structures. The reliability of the various assembly configurations was assessed in air-to-air thermal cycling and compared using a Weibull analysis. Reliability of Wafer-Level CSPs Compared to conventional CSPs, wafer-level CSPs are less likely to experience popcorning, die-substrate delamination delamination /de·lam·i·na·tion/ (de-lam?i-na´shun) separation into layers, as of the blastoderm. de·lam·i·na·tion n. 1. A splitting or separation into layers. 2. and other moisture-induced defects. However, the mechanical and thermal behavior of a wafer-level CSP is dominated by the silicon die. Therefore, a wafer-level CSP will typically have a coefficient of thermal expansion coefficient of thermal expansion, n See expansion, thermal coefficient. (CTE (Coefficient of Thermal Expansion) The difference between the way two materials expand when heat is applied. This is very critical when chips are mounted to printed circuit boards, because the silicon chip expands at a different rate than the plastic board. ) that is much lower than a traditional overmolded CSP. The wafer-level CSP is also stiffer and less compliant to thermally and mechanically induced stresses than most CSP designs. Package Description The device used for this assembly and reliability experiment did not require underfill. The package pads were routed to a 0.75 mm pitch using CSP-size balls. This device was intended for memory applications such as flash, DRAM, EEPROM (Electrically Erasable Programmable ROM) A rewritable memory chip that holds its content without power. Although EEPROMs spawned flash memory, EEPROMs are byte addressable at the write level, whereas flash chips must erase a block of bytes before rewriting. and SRAM See static RAM. SRAM - static random-access memory . The device was a true wafer-level package as it used standard semiconductor processing equipment to produce a thin-film redistribution layer and a wafer-level ball attach technology. The package contained a two-layer polymer dielectric dielectric (dī'ĭlĕk`trĭk), material that does not conduct electricity readily, i.e., an insulator (see insulation). A good dielectric should also have other properties: It must resist breakdown under high voltages; it should not system of benzocyclobutene (BCB BCB Banco Central do Brasil (Brazil's central bank) BCB Borland C++ Builder BCB Bangladesh Cricket Board BCB Benzocyclobutene (low loss dielectric substrate) BCB Bumiputra-Commerce Bank BCB Broadcast Band ) and a thin film solderable redistribution layer of Al/NiV/Cu. The device contained 46 solder solder (sŏd`ər), metal alloy used in the molten state as a metallic binder. The type of solder to be used is determined by the metals to be united. Soft solders are commonly composed of lead and tin and have low melting points. Hard solders (i. bumps distributed in an area array (6 by 8 pattern), depopulated de·pop·u·late tr.v. de·pop·u·lat·ed, de·pop·u·lat·ing, de·pop·u·lates To reduce sharply the population of, as by disease, war, or forcible relocation. at the center. The package was rectangular in shape with physical dimensions of 0.317 in. X 0.246 in. and a thickness of 0.0438 in. (from the top of the die to tip of the bump). The silicon die had an overall thickness of 0.027 in. and was attached to a 0.0003 in. flex layer. The Sn/37Pb solder bumps had an unassembled un·as·sem·bled adj. Made or manufactured with parts or sections ready to be joined or fitted together before use: working with unassembled metal shelving. diameter of 0.0215 in. and a height of 0.0165 in. The measured CTE of the package was approximately 4.5ppm/[degrees]C. The package was rigid and did not warp upon heating or cooling. Test Board The test board used in this experiment was a 0.041 in. thick, double-sided FR-4 substrate with four signal layers (two surface and two internal). The board was finished with an organic solderability preservative preservative Any of numerous chemical additives used to prevent or slow food spoilage caused by chemical changes (e.g., oxidation, mold growth) and maintain a fresh appearance and consistency. Antimycotics (e.g. (OSP (Online Service Provider) See online service. OSP - Optical Signal Processor ) to protect the copper pads. The glass transition temperature The glass transition temperature is the temperature below which the physical properties of amorphous materials vary in a manner similar to those of a solid phase (glassy state), and above which amorphous materials behave like liquids (rubbery state). of the board was 175[degrees]C, and the CTE was measured to be approximately 16 ppm/[degrees]C. Six land array patterns were utilized in the experiment. Three of the patterns contained standard, non-solder mask-defined (NSMD NSMD Non Solder Mask Defined (semiconductor substrate process) NSMD Non-State Market Driven (governance or regulation) NSMD Nonseasonal Mood Disorders ) pads with diameters of 0.011, 0.013, or .015 in. The remaining three patterns also contained NSMD pads with 0.011, 0.013 or 0.015 in. diameters, but each pad contained a 0.005 in. diameter (nominal) via. The via-in-pad structures were used to route the surface signal layer to an internal signal layer. The via-in pads were unfilled. Figure 1 contains images of the via-in-pad structures. Via misregistration is observed in the figure. Test Plan The main objectives of the experiment were to: * investigate assembly issues concerning the wafer-level CSP * compare solder paste Solder paste (or solder cream) is a mix of small solder particles and flux. It is used extensively in the automated soldering processes wave soldering and reflow soldering. assembly to flux assembly and effect on solder joint reliability * determine the feasibility of assembly on via-in-pad land patterns and compare the solder joint reliability to conventional NSMD pad connections * evaluate the effects of PCB pad size on the solder joint reliability for both conventional and via-in-pad structures. Assembly The wafer-level devices were assembled in two sets. Set 1 assembly followed a traditional CSP assembly process, while Set 2 assembly involved standard flip chip practices. A single reflow (1) The process of heating and melting the solder that has been screen printed onto a printed circuit board in order to bond chips and other components to the board. Surface mount chips (SMT) use the reflow method. Contrast with wave soldering. See also reflowable text. profile was developed for both assembly processes using a forced convection oven convection oven n. An oven having a fan that shortens cooking time by circulating hot air uniformly around the food. . [FIGURE 1 OMITTED] Prior to assembly, the wafer-level devices were baked at 125[degrees]C for 12 hours. This practice removes excess moisture from the packages and prevents popcorning and delamination. The test boards had been stored in sealed packages and were not baked prior to assembly. [FIGURE 2 OMITTED] Set 1 assembly utilized a no-clean, type IV Sn/37Pb solder paste with a 90% metal content. The paste was printed over the PCB pads using a stencil stencil, cutout device of oiled or shellacked tough and resistant paper, thin metal, or other material used in applying paint, dye, or ink to reproduce its design or lettering upon a surface. constructed from 0.005 in. thick stainless steel stainless steel: see steel. stainless steel Any of a family of alloy steels usually containing 10–30% chromium. The presence of chromium, together with low carbon content, gives remarkable resistance to corrosion and heat. foil. Polyurethane polyurethane Any of a class of very versatile polymers that are made into flexible and rigid foams, fibres, elastomers (elastic polymers), surface coatings, and adhesives. squeegees with a durometer hardness of 95 positioned at an angle of 60[degrees] were used to apply the paste to the test boards. A print speed of 15 mm/sec. and a print pressure of 0.49kg/in. resulted in excellent print deposits. The wafer-level devices were then placed on the PCB and reflowed in the forced convection oven. Set 2 assembly was performed by applying flux to the wafer-level devices through the use of a thin film applicator ap·pli·ca·tor n. An instrument for applying something, such as a medication. applicator, n a device for applying medication; usually a slender rod of glass or wood, used with a pledget of cotton on the end. (TFA TFA Teach For America TFA Thyroid Foundation of America TFA Trifluoroacetic Acid TFA Trans Fatty Acid TFA Two Factor Authentication (computer security authentication) TFA Texas Forensic Association TFA Total Fatty Acids ). The devices were dipped into a 0.0045 in. thick layer of no-clean tacky flux prior to placement. Once the devices were placed, the assemblies were run through the forced convection oven. No underfill was applied. Reflow was performed using a standard ramp-soak-ramp profile. The test boards and wafer-level devices were heated from room temperature to 165[degrees]C at a rate of 1.5[degrees]C/sec. The assemblies then dwelled at 165[degrees]C for approximately 140 seconds to allow for solvent evaporation evaporation, change of a liquid into vapor at any temperature below its boiling point. For example, water, when placed in a shallow open container exposed to air, gradually disappears, evaporating at a rate that depends on the amount of surface exposed, the humidity and flux activation to occur. The assembly temperature was then increased to a peak of 220[degrees]C at a rate of nearly 4.0[degrees]C/sec. The assemblies were then cooled to 85[degrees]C (exit temperature) at an average rate of 2.0[degrees]C/sec. This reflow profile resulted in a time above liquidus (183[degrees]C) of approximately 47 sec. and required 6m45s to complete. A reduced oxygen atmosphere was used throughout the reflow operation. Nitrogen gas ([N.sub.2]) was pumped into the oven so that the oxygen content was below 50 ppm. Post-Assembly Operations Electrical, visual and x-ray inspection techniques were employed to qualify the wafer-level assembly process. Probe testing with a multimeter An instrument for measuring electricity (volts, amps, ohms) that is widely used and available in numerous shapes and sizes. An analog multimeter displays results by moving a pointer across a printed scale. indicated that all assemblies were electrically good. The analysis also indicated that the various assembly combinations (PCB pad dimensions, paste or flux) had an insignificant effect on the average resistance of the daisy-chained assemblies. X-ray images of the assemblies did not reveal solder bridging, solder balling In BGA chip packages, it is the tiny globe of solder that provides the contact between the chip package and the printed circuit board. Also called a "solder bump." See BGA. or other defects. However, the solder joints formed on PCB via-in-pad structures contained voids. The voids were present in both the solder paste and flux-assembled devices. The x-ray images indicated that the voids were consistent in size (about 5% of the joint cross sectional area) and frequency (one void per joint). Thus, the void content was acceptable under the requirements of the IPC-7095 standard for BGAs. Void formation within the solder joints on the conventional PCB pads was minimal and not measured. Cross sectioning of representative assemblies was performed to study solder joint quality, standoff stand·off n. 1. A tie or draw, as in a contest. 2. A situation in which one force neutralizes or counterbalances the other. 3. A standoff insulator. adj. Standoffish. height and to examine the voids observed in x-ray. Cross sectioning revealed that the solder bumps had wet well to the conventional PCB pads and resulted in excellent solder joints that showed good collapse and metallurgical met·al·lur·gy n. 1. The science that deals with procedures used in extracting metals from their ores, purifying and alloying metals, and creating useful objects from metals. 2. bonding. Cross sections of the solder joints formed over via-in-pad structures indicated that the numerous voids observed by x-ray were the result of gasses trapped in the via opening during the reflow process. In many instances the void remained in the via, although solder was observed along the via floor and walls. Voids were less frequently encountered near the component attachment pad directly above the via. In these cases, the via was completely filled with solder. In all cases, the void diameter was nearly equal to the via diameter. Cross sectional images may be found in Figure 2. Standoff, or joint height was measured using a laser profilometer and by cross sectional analysis. Standoff is a function of package weight, I/O count, bump size, PCB pad dimensions, paste volume and other factors. The measurements strongly indicated that the standoffs of the flux-assembled devices were inversely related to the PCB pad diameters. A decrease in pad diameter results in the reduction of solderable pad area. This result, in turn, limits the amount of collapse that a solder bump may experience as it wets across the PCB pad. Thus, less collapse results in a taller solder joint. The paste assemblies evaluated did not produce the same trend. In fact, no significant difference was observed between the standoff heights of the devices assembled to the 0.011, 0.013, and 0.015 in. diameter PCB pads. This result is due to the fact that the stencil design for this experiment incorporated larger aperture An orifice. It often refers to an opening in which light is allowed to pass in optical systems such as cameras and lasers. See f-stop and numerical aperture. openings for the larger PCB pads. Therefore, more paste was applied on the larger pads, which compensated for the increase in solderable area. Overall, the paste assemblies produced greater standoff heights than similar flux assemblies. Standoff heights are summarized in Table 1. [FIGURE 3 OMITTED] Reliability Analysis Reliability of an electronic assembly or an individual component is "the ability to function for an expected period of time without exceeding an expected acceptable failure probability." Air-to-air accelerated testing is one of the more common methods used to evaluate the reliability of electronic components. The goal is to accelerate the time-dependent wear out failure mechanism of second-level solder fatigue, which is commonly encountered in field failures. The test used to evaluate the wafer-level assemblies was a 20-minute 0/100[degrees]C air-to-air thermal cycle consisting of five-minute dwell times The time cargo remains in a terminal's in-transit storage area while awaiting shipment by clearance transportation. See also storage. at the temperature extremes and 20[degrees]C/min. transition rates between the temperature extremes. The test specimens were monitored in-situ using a 256 channel event detection system (EDS (Electronic Data Systems, Plano, TX, www.eds.com) Founded in 1962 by H. Ross Perot (independent candidate for the President of the U.S. in 1992), EDS is the largest outsourcing and data processing services organization in the country. ). The EDS was programmed to record events or loop resistance measurements that exceeded 300 ohms for a minimum duration of 200 nanoseconds. Failure was defined as the cycle at which the first event was recorded that could be verified by nine additional events as described in IPC-SM-785. Failures were frequently removed from the thermal cycle to minimize further damage to the assembly. The suspect assemblies were electrically probed to isolate the probable failed joint. The assembly was then cross sectioned through the suspect joint and microscopically examined. The reliability of each sample set was calculated upon the completion of the thermal cycle test. Package reliability, or lifetime, is often reported by the number of thermal cycles required for 63.2% of a sample set to fail. The data are usually presented using two-parameter Weibull distributions In probability theory and statistics, the Weibull distribution[1] (named after Waloddi Weibull) is a continuous probability distribution with the probability density function Fit describes the data's deviation from a straight line. Single mechanism fatigue failures usually result in fits of 0.900 or greater. Slope, or beta values, describe the successive failure rate of the sample set. Greater slopes indicate faster fatigue rates, while a slope of less than one indicates a wear-in mechanism. N01 is the projected time (in cycles) required for 1% of the sample set to fail. The software package used to produce the Weibull plots utilized rank regression, which generally produces conservative reliability estimates. The results of the reliability analysis were used to compare the following: conventional pad vs. via-in-pad, flux assembly vs. paste assembly and PCB pad diameter. Results, Failure Analysis Seventy-two packages were subjected to the thermal cycle test. The first failure occurred at cycle 309. The wafer-level package had been assembled to the 0.013 in. diameter conventional pad array with solder paste. The failure location was electrically located, but cross sectional analysis failed to determine the cause of the early failure. The second-level solder joints were continuous and showed no indication of fatigue. The next failure would not occur until cycle 1756. The second failure was identified as second-level solder fatigue (Figure 3). The early failure had a significant impact on the reliability analysis of the wafer-level package. When included in the Weibull analysis, the predicted N01 of all the assemblies was 1,098 cycles. Exclusion from the analysis substantially increased the N01 to 1,500 cycles. However, the early failure had little impact on the N63.2 value (3,035 vs. 3,008 cycles). The Weibull reliability analysis is summarized in Table 2. Note that the early failure was excluded from the analysis because the failure mechanism was not positively identified. [FIGURE 4 OMITTED] Several trends are apparent from the data analysis summarized in Table 2: * The packages assembled on via-in-pad structures produced an N63.2 16% greater than those assembled on conventional pads. Hypothesis analysis determined that the difference was significant. * Reducing pad diameter improved solder joint reliability. Decreasing the pad diameter from 0.015 to 0.011 in. increased the N63.2 by an average of 35%. Hypothesis analysis determined that the difference was significant. * No significant reliability difference was observed between packages assembled using solder paste and those assembled with flux with pad design constant. Flux assemblies actually produced slightly greater N63.2 values. Cross-sectional analysis Cross-sectional analysis Assessment of relationships among a cross-section of firms, countries, or some other variable at one particular time. revealed that the package failure mode was predominantly solder fatigue. The fatigue failure occurred through the bulk solder material near the component attachment pad, independent of the board pad size or type. The crack formations were very fine, originating at the solder joint corners and propagating toward the solder joint center. Electrical mapping of the failed samples showed that the solder joints containing severe fatigue were located at the outer corner of the package where the distance to neutral point (DNP DNP n. Deoxyribonucleoprotein; a complex of DNA and protein that usually yields DNA upon cell disruption and isolation. DNP 2,4-dinitrophenol. ) was maximum. Dye penetration tests A test of a network's vulnerabilities by having an authorized individual actually attempt to break into the network. The tester may undertake several methods, workarounds and "hacks" to gain entry, often initially getting through to one seemingly harmless section, and from there, (Figure 4) were performed, and the results supported the observations made by cross sectional and electrical analysis. Conclusions This experiment revealed the following conclusions: * Wafer-level devices can be assembled in high yield using standard surface-mount practices. * Solder joint reliability on via-in-pad features was equivalent to that on conventional pads. * Decreasing pad diameter from 0.015 to 0.011 in. improved reliability more so than assembly with paste in place of flux. * Joints assembled to via-in-pad structures contained a void due to gasses trapped in the via. The presence of the void did not reduce the reliability of the solder joint.
TABLE 1: Average standoff heights.
Pad Type Assembly PCB Pad Diameter
0.011" 0.013" 0.015"
Conventional Flux 0.0127" 0.0123" 0.0118"
Conventional Paste 0.01325" 0.01325" 0.01325"
Via-in-Pad Flux 0.01275" 0.0126" 0.0125"
Via-in-Pad Paste 0.0135" 0.01375" 0.0138"
TABLE 2: Weibull analysis summary.
Pad Type Assembly Pad Diameter N01 (Cycles)
All All All 1500
Conventional All All 2749
Via-in-Pad All All 3206
Conventional Flux 0.011" 2292
Conventional Flux 0.013" 2155
Conventional Flux 0.015" 1795
Conventional Paste 0.011" 2544
Conventional Paste 0.013" 1148
Conventional Paste 0.015" 1385
Via-in-Pad Flux 0.011" 2595
Via-in-Pad Flux 0.013" 2544
Via-in-Pad Flux 0.015" 1979
Via-in-Pad Paste 0.011" 2362
Via-in-Pad Paste 0.013" 1982
Via-in-Pad Paste 0.015" 1734
Pad Type N63.2 (Cycles) Beta [r.sup.2]
All 2035 4.524 0.978
Conventional 1334 6.364 0.952
Via-in-Pad 1957 9.325 0.935
Conventional 3205 13.73 0.926
Conventional 2676 21.22 0.903
Conventional 2277 19.35 0.781
Conventional 3131 22.19 0.928
Conventional 2582 5.677 0.856
Conventional 2028 12.05 0.891
Via-in-Pad 3368 17.63 0.935
Via-in-Pad 3496 14.48 0.992
Via-in-Pad 2780 13.54 0.781
Via-in-Pad 3472 11.94 0.931
Via-in-Pad 3047 10.69 0.922
Via-in-Pad 2785 9.711 0.811
Michael Meilunas is a process research engineer with Universal Instruments Corp., Binghamton, NY; email: meilunas@uic.com; Parvez Patel is a senior engineer, business processes, with Motorola, Inc., Libertyville, IL; email: parvezpatel@motorola.com. |
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