Aspec Technology Rolls Out New EDA Software Tools; First Tools to Accurately Address Worst Case 2-D and 3-D Interconnect Modeling.

SUNNYVALE, Calif.--(BUSINESS WIRE)--Dec. 15, 1999--

Aspec Technology, Inc., (Nasdaq:ASPC), an innovator of productivity solutions for the Electronic Design Automation (EDA) and Product Data Management (PDM) markets, announces the first available technology to address statistically-based worst case interconnect modeling for deep submicron designs.

The patent pending Statistically-based Worst case Interconnect Model (SWIM) generator and Interconnect delay Calculator (InterCal) products will give semiconductor manufacturers the ability to enhance performance, maximize capacity, optimize power consumption and improve overall yield by allowing designers to use more accurate worst case interconnect models.

SWIM and InterCal provide extremely accurate 2-D and 3-D statistically-based worst case interconnect modeling and pre-layout interconnect data for deep submicron design and process development. Most manufactures use worst case process variations (skew corner worst case model), which provide pessimistic models, and therefore causes wide, unrealistic design margins for chip designers. By using statistically-based worst case interconnect modeling, an accurate estimation can be made of the process variation and therefore designers can take greater advantage of deep submicron technology without the risk of failing chips.

Dr. Soo-Young Oh, chief technologist at Aspec stated, "In deep submicron technology, the on-chip interconnect delay can account for more than 70 percent of the total delay in determining chip performance. Foundries currently use nominal or skew corner delays to estimate interconnect delays. This approach significantly under estimates the performance of circuits, which impacts the overall performance and potential yield. With a statistically worst case interconnect modeling approach, significant performance increases can be achieved for the same process. By using SWIM and InterCal, engineers will now be able to accurately model interconnect using worst case modeling techniques without sacrificing performance, capacity or yield."

Dr. Oh has been involved with process technology research and tool development for 17 years. He has pioneered and is the industry leader in the interconnect modeling of deep submicron processes and high-speed microprocessor chips. Dr. Oh has also successfully developed the 2D/3D R, L, C simulator, Raphael and licensed it to TMA.

Dr. Jeong-Taek Kong, Senior CAD manager at Samsung Electronics Ltd. stated, "Parasitic extractions which takes into account process variations, is extremely important in 0.18um technologies and below. We have found that SWIM is the only solution that provides the practical methodology and meets our requirements for optimum worst-case verifications. It provides the accuracy as well as the flexibility required for high performance designs."

With the number of designs targeted for 0.18um technology and below increasing at 24 percent CAGR rate over the next four years, the demand for SWIM and InterCal type technology is also forecasted to grow exponentially. With the high cost of fab development and optimization, semiconductor manufacturers can now leverage more out of each technology generation through more accurate modeling techniques such as SWIM.

Product availability:

SWIM and InterCal are released and currently available to customers.

About Aspec Technology:

Aspec Technology, Inc. (Nasdaq:ASPC) is a provider of advanced software solutions, which dramatically increase design. Aspec's Silicon Intelligent(TM) Electronic Design Automation (EDA) tools address key deep submicron design and verification problems for complex Integrated Circuits (IC) and systems. Aspec's Inbox Software provides Internet-based, business-to-business, content management software solutions, which shorten time-to-market by managing product content and the business processes required to deliver and maintain content throughout the product lifecycle -- from concept to end-of-life. Aspec is located at 830 East Arques Avenue, Sunnyvale, CA 94086. More information is available at www.aspec.com.

This news release contains forward-looking statements related to Aspec which are based on current expectations that includes statements regarding the Company's future expectations, beliefs, hopes, intentions, and strategies. These forward-looking statements may involve substantial risks and uncertainties. Actual results and developments therefore may differ materially from those described in this release. For more information about Aspec and risks arising when investing in Aspec, you are directed to Aspec's most recent reports on Form 10-Q and registration statement on Form S-1 as filed with the United States Securities and Exchange Commission.