Aspec Enters EDA with Two Strategic Acquisitions; IC Design & Verification Tools Leverage Aspec's Experience in Semiconductor Technology.SUNNYVALE, Calif.--(BUSINESS WIRE)--Sept. 9, 1999-- Aspec Technology, Inc. (Nasdaq:ASPC ASPC Associated Students of Pomona College (Claremont, California) ASPC American Shetland Pony Club ASPC Arizona State Prison Complex ASPC Algorithmic Statistical Process Control ASPC Attached Shuttle Payload Center ), a provider of very deep submicron system-on-chip (SOC) technologies and silicon intelligent design tools, today announced that it has acquired two EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. start-ups: Chip & Chip, Inc., and Verilux Design Technology, Inc., which are focused on providing solutions for emerging physical design challenges in complex SOC IC development. The acquisitions are primarily stock for stock transactions. Specific financial terms of the acquisitions will be disclosed in the upcoming quarterly financial statement. Conrad J. Dell'Oca, chairman of the Board and co-founder of Aspec, said of the acquisitions, "The acquisitions clearly mark a new era in Aspec's history, where we leverage our extensive experience in semiconductor process and technology to provide advanced EDA tools to solve key design problems. These design tools will effectively compete in deep submicron IC and SOC designs for market segments such as wireless and networking." Each generation of semiconductor process advance brings new challenges in how integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for (IC) designers model, integrate, simulate, and verify the entire chip. These challenges provide significant new opportunities that will launch next generation EDA companies  The external links in this article or section may require cleanup to comply with Wikipedia's content policies. . In the sub-0.18micron micron: see micrometer. One micrometer, which is one millionth of a meter or approximately 1/25,000 of an inch. The tiny elements that make up a transistor on a chip are measured in micrometers and nanometers. See process technology. generations, the challenge has become how to efficiently integrate complex, yet subtle, device and interconnect (1) To attach one device to another. (2) A physical port (plug, socket) or wireless port (transmitter, receiver) used to attach one device to another. physics into EDA software that can effectively handle millions of transistors. Aspec believes that its deep understanding of these device physics issues combined with its SIP and complex design expertise can be turned into EDA breakthroughs. The acquisition of these two companies unites two leading EDA software developers with Aspec's strong IC technology and experience. Dr. Soo-Young Oh, Vice President of R&D of Verilux, is a world-renown interconnect expert who developed at Hewlett-Packard what eventually became Avanti's Raphael tool. Raphael has gained the reputation in the EDA industry as the most accurate modeling tool for semiconductor processes. William (Wai-Yan) Ho, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Chip & Chip, is a well known EDA entrepreneur who founded two EDA companies, which developed the Cedar cedar, common name for a number of trees, mostly coniferous evergreens. The true cedars belong to the small genus Cedrus of the family Pinaceae (pine family). and Arcadia tools. Arcadia, a tool which was sold to Synopsys' Epic subsidiary, has become known as a very fast and accurate interconnect RC extraction tool for deep submicron SOC designs. "The combination of Verilux and Aspec gives us critical experience and knowledge base on how to roll out our inductance-aware IC verification tools," commented Dr. Soo-Young Oh. "We are very excited to leverage Aspec's semiconductor process, design and SIP expertise with Chip & Chip's IC design/verification software innovations," said Ho. "We expect to introduce software which takes new approaches to solving difficult physical IC design problems for 0.18micron process and beyond." About Chip & Chip Chip & Chip, Inc. was founded in 1998 by William (Wai-Yan) Ho and Frank (Chong Ming) Lin to address critical physical design challenges in System-on-Chip (SOC). Together, the two founders have over 40 years of experience in Integrated Circuit and EDA software development. Chip & Chip is currently located at 4655 Old Ironsides Old Ironsides: see Constitution, ship. Old Ironsides the frigate Constitution, symbol of U.S. success in War of 1812, now preserved as a museum. [Am. Hist.: Benét, 733] See : America Drive, Suite 420, Santa Clara Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , CA. About Verilux Verilux Design Technology, Inc. was founded in 1997. Its founder, Dr. Soo-Young Oh developed at Hewlett-Packard what eventually became Avanti's Raphael tool, considered to be the most accurate model of the semiconductor process. Verilux is currently located at 4633 Old Ironsides Drive, Suite 460, Santa Clara, CA. About Aspec Technology Aspec Technology, Inc. (Nasdaq:ASPC) is a provider of semiconductor intellectual property (SIP) libraries, advanced EDA tools and design services for complex IC (Integrated Circuit) system design and development. Aspec is located at 830 East Arques Avenue, Sunnyvale, CA 94086. More information is available at http://www.aspec.com. This news release contains forward looking statements related to Aspec which are based on current expectations that includes statements regarding the Company's future expectations, beliefs, hopes, intentions, and strategies. These forward looking statements may involve substantial risks and uncertainties. Actual results and developments therefore may differ materially from those described in this release. For more information about Aspec and risks arising when investing in Aspec, you are directed to Aspec's most recent reports on Form 10-Q Form 10-Q See 10-Q. and registration statement on Form S-1 as filed with the United States United States, officially United States of America, republic (2005 est. pop. 295,734,000), 3,539,227 sq mi (9,166,598 sq km), North America. The United States is the world's third largest country in population and the fourth largest country in area. Securities and Exchange Commission. Acronyms: EDA: Electronic Design Automation IC: Integrated Circuit IP: Intellectual Property SIP: Semiconductor Intellectual Property SOC: System-on-Chip |
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