Asian test symposium; proceedings.9780769526287 Asian test symposium; proceedings. Asian Test Symposium (15th: 2006: Fukuoka, Japan) Computer Society Press 2006 451 pages $215.00 Paperback TK7870 These 63 papers selected for the November 2006 symposium explore techniques for testing integrated circuits and systems, and are divided into sessions on test power reduction, memory tests, design verification, scan test methods, defect diagnosis, analog DFT, solutions for jitter problems, test compression, and network issues. Topics include a BIC BIC See: Bank Investment Contract sensor capable of adjusting IDDQ IDDQ Indefinite Delivery Definite Quantity IDDQ Integrated Circuit Quiescent Current limit, test pattern generation for testing signal integrity, the diagnosis of transistor shorts in a logic test environment, and automation of IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1149.6 boundary scan synthesis in an ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. methodology. No subject index is provided. ([c]20072005 Book News, Inc., Portland, OR) |
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