Asia upswings with MEMS R&D and microsystems assembly.

Asia is the crossroads where the yin of high technology meets the yang of high-volume manufacturing. Lately, microelectromechanical systems (MEMS) and die-based products assembly have gathered momentum here. Fueled by high-speed communication, networking and other emerging and esoteric applications, these areas are being deemed the next big wave in Asia by the electronics industry.

According to a recent report, "the worldwide MEMS/MST market is currently estimated at $11 billion.... By 2007, market revenues will exceed $26 billion ... growing at an AAGR of 19.1 percent." (1) Similar headlines have dominated other technology media as well. MEMS and microsystems technology (MST) include devices such as inertial sensors and accelerometers for automotive applications; ink jet printer heads; radio frequency (RF) filters for cell phones; high-speed communication; micro optical and optoelectronic systems; flow sensors; micro fluid pumps and micro-motor controllers.

Advanced package assembly approaching true die size (TDS) and direct chip attachment (DCA) brings together high performance and reliability. However, the principle challenge to low cost realization remains high yield, requiring fundamental research into materials and assembly process development. As the microsystem assembly focus changes in Asia, communications and multilevel die stack interconnection sectors are visibly moving to meet increasing product performance while shrinking product size.

MEMS, Microsystems Packaging and Asian Consortiums

As the window of opportunity opens, institutes and research bodies in Asia are preparing by developing core competencies and acquiring education in MEMS, including: nanoimprinting, aligned bonding methodologies, process flow and wafer-level testing. In China and Taiwan, MEMS are regarded as the one of the major engines for technology growth. Both countries are focusing on MEMS research and technology development via universities and research facilities. Taiwan has initiated government programs to keep abreast of international developments in this field.

Singapore's research initiatives have recently been restructured to focus on emerging trends in science, engineering and the biomedical field. The Science & Engineering Research Council (SERC), one of the four principle arms of the Agency for Science, Technology and Research (A STAR), oversees the research and development (R&D) initiatives of seven major Singapore Research Institutes (RIs), many of which are involved in MEMS R&D activities, albeit from different perspectives.

The Data Storage Institute (DSI), for example, is pursuing MEMS actuators and sensors for motion and motionless magnetic and optical data storage and for disk drives. The Institute of Materials Research & Engineering (IMRE) is conducting work on materials related to electro-optical MEMS, including fabricating structures such as beams, cantilevers and membranes. The Institute of Microelectronics (IME), which specializes in silicon-based structures--and has been involved with MEMS R&D since 1993--is currently pursuing MEMS design, process, packaging and application specific integrated circuit (ASIC) development. The Singapore Institute of Manufacturing Technology (SIMTech), formally known as Gintic, is another key institute involved in MEMS and microsystems packaging research.

In a mandate revised at the end of 2001, SIMTech shifted its focus from mainstream electronics packaging and surface-mount assembly towards MEMS, microsystems packaging and subsystems, including optical switch and RF components, micro power generation systems and low temperature co-fired ceramics (LTCC). The revised program aims to develop core competencies ha MEMS design modeling, fabrication, packaging and system integration. Extensive collaboration with leading universities, research institutes and companies has been established. Research partners include National University Singapore (NU), Nanyang Technological University (NTU), Institute of Microelectronics (IME), Institute of Materials Research & Engineering (IMRE), Institute of Micro Technology (IMT) of University of Neuchatel, Esashi Lab of Tohoku University and Shanghai Institute of Microsystems and Information Technology.

In the past, IME and SIMTech collectively accounted for around 20 consortia in the field of microelectronics and packaging development. Twelve consortia involving 172 companies have formed since 1993. The high-density substrate (HDF) consortium consisted of two parts; the first involved members--such as 3M, Agilent Technologies and United Test & Assembly Services--in the design of three package substrate types extending to flex ball grid arrays (FBGAs), plastic ball grid arrays (PBGAs) and flip chips. In the second part, participating local enterprises and multinational corporations (MNCs), including Matsushita Technologies, Gul Technologies and M-Flex Singapore, addressed high-density board fabrication with a variety of substrate materials.

Developments included multilayer high-density substrates with 50 Inn space features and microvias in the micron range on a variety of substrate materials. A newly established Electronics Packaging Program aims to develop seamless interconnection technologies, advanced substrate manufacturing processes and reliability methods in RF, digital broadband and optoelectronics applications. The research partners for this program include: the Korea Advanced Institute of Technology; National University of Singapore; Nanyang Technological University; the Broadband Consortium and the Advanced Substrate and Integrated Passives Consortium.

The results produced by such consortia are an excellent example of how key Asian regions are developing internal resources. The consortium approach benefits electronic industries, electronics manufacturing services (EMS) companies and subcontractors with the know-how to leverage cutting-edge technologies in the electronic packaging and assembly field.

Miniaturizing Trends and the Assembly Process Paradigm

Asia is not only one of the world's largest cell phone markets but also the largest producer of cell phones. Miniaturizing trends are most visible in this segment. Although cell phones account for some 20 percent of the total communications products manufactured, they account for almost 40 percent of the die product usage--mainly on account of the required size-performance index. Cell phone assembly is an excellent benchmark to indicate the scale of process development and equipment upgrades that a printed circuit board (PCB) assembly operation needs over a short time span to keep current with miniaturizing trends.

Cell phone architecture is typically implemented using 8 to 14 integrated circuits (ICs) with an active device footprint area (total die area) of around 3 sq. cm. Within a few years, functionality and performance have almost tripled, the phone size and PCB area have shrunk by 25 to 30 percent and substrate thickness has been halved. The assembler's major challenge lies in coping with the package footprint reduction from 20 sq. cm. for earlier phones to less than 9 sq. cm. for current phones.

Figure 1 compares a G1 set from 1997 with a G2 set made around the year 2000. The G1 has predominantly large quad flat packs (QFPS), plastic leaded chip carriers (PLCCs), small outlines (SOs) and thin small outline packages (TSOPs), with a mixture of size 1206 and 0805 passives. In contrast, the G2 shows many new technology packages--such as wire bond chipscale packages (CSPs), chip array devices, a flip chip CSP, quad flat non-leaded and other leadless devices--and the passives are predominantly 0603s and 0402s. Assembly challenges are even greater in the current G2.5 phones, with more new technology devices and possibly 0201 passives. G3 phones, which are just around the corner, have 10 times the complexity and rely largely on one or more forms of multi-chip stacks or multichip packages (MCP). One package from Fujitsu has stacked as many as eight dies, requiring die thinning down to 0.025 ram.

[FIGURE 1 OMITTED]

While wafer-level integration continually migrates many of the functional blocks from the PCB onto the die, its domain are blocks ideally realized in the same type of fabrication technology. On the other hand, MCPs bring together dies from a diverse range of technologies and suppliers to optimize the device function. In the end, such approaches pave the way for greater functionality, high data rate messaging and Internet, built-in digital still and video image capture, larger color LCD displays and videoconferencing capabilities. Although ergonomics limits further external size reductions on phones, the constant reduction in die packaging ratios and high packaging efficiencies continually pose challenges for any surface-mount assembler.

In a Nutshell

Asia is responding to the technological challenge of MEMS and MST. Asian industries are taking interest and nurturing these fields with revised initiatives and focus, viewing MEMS and microsystems packaging as significant enablers to industry growth. In the area of die-based products, Asia is developing technologies with many visible spin-offs. Wafer bumping and on-wafer redistribution services are expanding in scope, solder flip chip technology is being used in multi-chip packages and products with high packaging densities incorporating Blue Tooth, Internet access, GPS, video and other applications are being assembled in Asian plants. The message is clear--manufacturers are shedding their old, rigid ideas and incorporating fresh approaches by giving development and education high priority.

A Special Note of Thanks

This column resulted from a meeting with Circuits Assembly editor Lisa Hamburg at the GlobalTronics conference last September in Singapore. My thanks to Lisa and the Circuits Assembly team for providing an avenue to share some first-hand observations on emerging technical trends and strategies in Asia.

References

1. Business Communications Company. RG8 270 MEMS Technology: Where To? www.bccresearch.com/editors/RGB-270.html.

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