As first design automation member of SEMI SEMATECH, Cadence joins focus on deep submicron IC design challenges; Capital & technical requirements of 0.35 and smaller submicron processes drives SEMATECH to dual focus on design & manufacturing.

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 20, 1995--Citing the significant technical and business challenges posed by next-generation deep submicron silicon processes, Cadence Design Systems Inc. Monday announced that it had joined SEMI/SEMATECH, the consortium of U.S. suppliers to SEMATECH and the U.S. semiconductor industry.

As the first electronic design automation (EDA) member of SEMI/SEMATECH, Cadence highlighted the fundamental changes the electronics industry faces in producing deep submicron integrated circuits (ICs), and the need for an EDA Technology Roadmap initiative to parallel the Semiconductor Industry Association's (SIA's) National Technology Roadmap for Semiconductors.

"Deep submicron technology has profound implications for IC design and even the overall IC business model," said Jon Cornell, senior vice president of business development at Cadence. "New submicron fabs cost a billion dollars, and need to generate something like $10M of revenue per day to be economically viable. This means design cycles and yield optimization efforts need to accelerate, both of which create a critical role for the EDA industry.

"By joining SEMI/SEMATECH, Cadence will work side-by-side with SEMATECH, its members and other SEMI/SEMATECH members to proactively define an EDA Technology Roadmap for the technology, complexity and productivity challenges of next-generation IC design."

In addition to collaborating with SEMI/SEMATECH's 182 members on the requirements for 0.25 and 0.18 micron processes, Cadence will actively participate in SEMATECH's recently formed Design Focus Technical Advisory Board (FTAB), as well as in pre-competitive research, industry workshops and roundtables.

SEMATECH's Design FTAB has identified timing-driven design as its first priority, closely followed by design-for-test, software interoperability, Design Cost of Ownership (DCoO) and Design Resource Models (DRM). Given that SEMATECH's member companies produce 80% of the silicon in the U.S. semiconductor industry, SEMATECH's design priorities will play a key role in defining the next-generation strategy and technology for EDA.

SEMI/SEMATECH's design focus reflects the huge ROI of EDA Software

SEMI/SEMATECH's addition of Cadence as a member is one of the first steps in expanding its focus to include the critical role of design automation in silicon viability and overall profitability. Given that process technology has achieved a 4x density improvement every three years, SEMATECH member companies now target design productivity and sophistication as critical for success.

"We are looking at what could be a major crisis for productivity," said Glen Cheney, president of SEMI/SEMATECH. "Although it is not completely understood by the industry, process technology is beginning to outstrip our capabilities to design."

Wil Shurtleff, director of design at SEMATECH, explained what the design capability gap could mean for SEMATECH member companies. "Unless we make dramatic improvements in design automation, we could risk at least a 4x increase in NRE (non-recurring engineering) costs. We've got a major disconnect coming -- in order to track the SIA Roadmap, we will need a 64x improvement in design productivity by the year 2000."

Paradoxically, SEMATECH's concern about a design technology gap comes at a moment of historic success for the semiconductor industry. With record earnings, and having met its goal of eclipsing Japan in the semiconductor market, Shurtleff said SEMATECH companies risked becoming complacent about next-generation challenges.

"Since SEMATECH member companies are already working on huge 0.35 micron design prototypes, it won't be long before we need to bring 0.25 micron into production. Improvements in semiconductor equipment and manufacturing technology are not enough. Both customers and suppliers need to work together to find new sources for asset productivity improvements," said Shurtleff. "Since Cadence provides the industry's most widely used IC design software, we welcome their collaboration in defining and creating the IC design environment for the future."

SEMI/SEMATECH is a national consortium of majority U.S.-owned and controlled manufacturing equipment, processing materials, software, and service suppliers to the semiconductor manufacturing industry. SEMI/SEMATECH was formed in concurrence with SEMATECH (SEmiconductor MAnufacturing TECHnology), the government/industry consortium established in 1987 by the U.S. Congress in response to growing national concern over the United States' competitiveness in the manufacture of advanced microelectronics. SEMI/SEMATECH is located at SEMATECH in Austin, Texas.

Cadence Design Systems Inc. is the worldwide leader in the development and marketing of design automation software and services that accelerate and advance the process of designing electronic systems. Cadence combines leading-edge technology with a complementary set of services that enable customers to improve the quality and time-to-market performance of innovative electronic products. Cadence is based in San Jose and employs approximately 2,400 people in research and development, sales and support locations worldwide. The company is listed on the New York Stock Exchange under the symbol CDN.

CONTACT: Cadence Design Systems Inc.

Anne Carr, 408/894-3429

Michael Busselen, 408/944-7339