Arithmatica Licenses Verific HDL Component Software; Arithmatica's CellMath Tools Now Include Verilog Interface for Streamlined Verilog IC Implementation Flow.ALAMEDA, Calif. -- Verific Design Automation today said that it has licensed its hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) Component Software to Arithmatica Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. (ICs). Arithmatica has integrated Verific's Verilog parser A routine that analyzes a continuous flow of text-based input and breaks it into its constituent parts. See parse. (language) parser - An algorithm or program to determine the syntactic structure of a sentence or string of symbols in some language. and register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) elaborator with its CellMath tools to provide tighter flow integration for Verilog users. The newly released CellMath Verilog interface feature provides Verilog designers familiar and easy-to-use syntax to specify robust datapath structures. The Verilog input language utilizes pragmas to explicitly instantiate In object technology, to create an object of a specific class. See instance. instantiate - instantiation advanced arithmetic datatypes such as carrysave wires and features such as internal rounding. Additionally, the companies have worked jointly on partitioning datapath logic within a logic module for synthesis in CellMath Designer, further streamlining the Verilog hardware designer's implementation flow. "Verific's best-in-class component software solutions allow us to offer Verilog support to our customers, which we would not have been able to do on our own," says Tony Curzon Price, Arithmatica's chief executive officer. "Verific is a company dedicated to excellence in customer support, top-quality HDL software and serves a formerly underserved EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. component software market segment." "Arithmatica has a unique product offering and a considerable market opportunity," notes Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. . "We're delighted to work with Arithmatica and give its customers Verilog input language support." About Arithmatica Arithmatica is the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, such as those used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing. Its unique technology, available through its tools products and design services, provides differentiated improvement to licensees' ICs. The company received its first venture funding in 2001 and is headquartered in Warwick, UK, with sales and support operations in Palo Alto, Calif. For further information about how its silicon math solutions increase silicon efficiency and boost productivity, please visit: www.arithmatica.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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