ArchPro Offers Fully Functional Mixed-Language Support for Multi-Voltage Simulator.Verific HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. Component Software Acts as Front End to MVSIM ALAMEDA, Calif. -- ArchPro today said its Multi-Voltage Simulator (MVSIM), an electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tool for pre-tapeout verification of power-managed designs, offers fully functional mixed-language support. This support for the Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. languages is made possible by hardware description level (HDL) Component Software from Verific Design Automation that serves as the front end to MVSIM. ArchPro initially licensed the VHDL parser and static elaborator, and recently added Verilog Component Software. Verific's HDL component software packages, delivered to ArchPro as source code, are written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms for both 32- and 64-bit compilers. ArchPro CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and chairman, Pratap Reddy, notes: "When looking for Looking for In the context of general equities, this describing a buy interest in which a dealer is asked to offer stock, often involving a capital commitment. Antithesis of in touch with. software to serve as a front end to EDA design tools, Verific is the first name that comes up every time. And, for good reason -- its products are easy to integrate and offer good value. With Verific serving as MVSIM's front end, users can be assured quality and high performance verification." MVSIM enables users to make system-level architectural decisions at RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; related to multi-voltage techniques including dynamic voltage scaling, power gating, and back bias. It works with popular simulators like ModelSim, NC-Sim, and VCS (1) (Verilog Computer Simulator) See Verilog. (2) (Version Control System) See version control. enabling users to verify multi-voltage designs at the RTL level. "ArchPro is serving a previously unmet need in the market with its low-power, multi-voltage simulator," comments Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. . "It gives us great pride to be part of a solution that will help designers meet the demanding 90- and 65nm power challenges." About ArchPro ArchPro provides EDA products to meet low-power and multi-voltage design challenges facing 90/65nm SoC designers. Having launched many of the world's first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk, and time to market for chip designers. Products support all major complementary IC / SoC design technologies. Privately held ArchPro is based in San Jose, Calif. www.archpro-da.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. ArchPro and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services. |
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