ArchPro Brings to Market World's First EDA Products for Multi-Voltage Verification and Implementation of Low-Power IC/SoC Designs.

SAN JOSE, Calif. -- MVRC and MVSYN Enable Verification and Implementation, Respectively, of Voltage States in Simple and Cost-Effective Comprehensive Solution

ArchPro Design Automation, Inc., a leading developer of Electronic Design Automation (EDA) solutions for low-power, multi-voltage Integrated Circuit (IC) and System-on-a-Chip (SoC) design, today announced two new industry-first products to aid with multi-voltage design processes. The two new products allow designers for the first time to verify voltage states and implement voltage states at the mere push of a button. They combine with ArchPro's MVSIM product to form the first available complete EDA solution for the entire chain of power management design cycles.

One of the new products, MVRC, is a Voltage Rule Checker that can catch errors in power managed designs, right at the RTL level. The second product unveiled, MVSYN, can modify the RTL to support as many voltage states as needed. Both tools can be used at the RTL or gate level and work with all major industry standard flows to give users a cost-effective method to reduce design cycles, design costs and speed time to market.

Bugs are often found in power management schemes after silicon is spun, causing time and cost-consuming revisions to silicon, system functions and software. ArchPro's comprehensive power management EDA offering now consists of MVRC and MVSYN as well as MVSIM. MVSIM, when announced in August 2005, was the world's first product to allow for verification, through simulation, of power management schemes prior to silicon spins. Combined, the products create a complete EDA environment to manage power designs, correct errors and verify low-power designs. The results include cost savings tied to reduced design cycles that also lead to a faster time to market.

MVRC also accomplishes another industry first by being able to prove that RTL and Netlist are equivalent, in conjunction with third-party equivalence checkers. Designs that pass regular equivalence checks in reality often have not. MVRC analyzes the design in all states to enable multi-voltage equivalence checking.

MVSYN, on the other hand, focuses on the pain that designers are facing over implementing multiple voltages. A number of vendors focus on reference flows with lots of scripts, at the Netlist stage, which is too late to understand the real impact on timing/area. So, designers end up having to hand-code the level shifters and isolation gates. Often, there are hundreds of scripts and elaborate methodology to organize directories, etc., and intense manual coordination at island interfaces for any changes. MVSYN solves this time-consuming, painstaking problem. MVSYN can eliminate months of RTL hand-coding work for customers and can insert thousands of devices as needed, all at the push of a button.

Power management isn't as simple as clock gating anymore. Designers often resort to Multiple Voltage Islands (including power gating) to control power. All the decisions related to voltage islands are done at the architectural level. Most tools on the market do some perfunctory topological checking at the Netlist level for the presence of appropriate level shifters, but that is hardly adequate because there is a lot of user setup and intervention required.

"ArchPro's comprehensive power management EDA suite offers an effective method to reduce costs and time associated with the design cycles of low-power IC verification and implementation," commented Michael Hurlston, Vice President and General Manager for WLAN Business, Broadcom. "The tool provides an elegant solution to power management design and offers a path to reducing time to market."

"Given that power management has become a key viability aspect of ICs, we find that customers are struggling with traditional flows, performing many tasks manually," said Pratap Reddy, Chairman and CEO of ArchPro. "Our solution significantly improves TTM for our customers by automating these tasks and eliminating errors right at the RTL level. Most errors emanate from voltage states and transitions between them. ArchPro is the only EDA vendor who can rigorously deal with voltage changes in quick time. We are using our unique technology to identify these errors, right up front. Even before users write a single vector, they have feedback on the power management architecture."

Availability

MVRC and MVSYN are available today, worldwide. MVSIM was available starting in August 2005. Pricing varies by configuration. ArchPro utilizes a direct sales force and plans to have distributor/reseller arrangements in some geographies. ArchPro's integrated power-based EDA solution is giving designers the tools to deal with voltage states painlessly, whether they are doing on/off of domains or DVFS, Power Gating, Back Bias or retention, by automating the most painful aspects of power management. This is accomplished by leveraging the user's existing tool suite with ArchPro's offerings to provide truly revolutionary design, cost, time and verification benefits.

About ArchPro

ArchPro has emerged as an inventive leader in EDA products to meet low-power and multi-voltage design challenges facing 90/65nm System-on-a-Chip (SoC) developers. Having launched many of the world's first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk and time to market for chip designers. Products also support all major complementary IC/SoC design technologies. ArchPro is a privately held venture capital funded company based in San Jose. The company has established an advanced R&D center in Bangalore, India, named PowerPlay Automation (India) Pvt. Ltd. More information about the company can be found online at http://www.archpro-da.com.

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