Aptix Improves System Explorer With Automated Mapping and Debugging Software for Rapid Integration and Validation of SoC Designs.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--May 21, 2001 Design Pilot Maps SoC Netlists into Programmable Logic Technology for Fast SoC Emulation Setup Aptix Corporation, a system integration, verification and validation Verification and Validation (V&V) is the process of checking that a product, service, or system meets specifications and that it fulfills its intended purpose. These are critical components of a quality management system such as ISO 9000. company, announced today that its System Explorer(TM) improves its SoC design mapping with a new version of Design Pilot.(TM) Design Pilot V2.0 improves the time-to-emulation for Register Transfer Level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) designs from weeks to days. Design Pilot offers an automated software environment that enables fast, efficient and predictable creation of prototypes for SoC devices directly from the RT-level of abstraction. It directs the compilation of a design for emulation directly from its RTL representation and uses popular synthesis tools such as those from Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ). As a front-end tool for Aptix's System Explorer, Design Pilot maps RTL design descriptions to programmable logic See PLD. netlists by incorporating logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. and hierarchical partitioning functions within an intuitive, wizard-like graphical user environment. It creates a netlist for in-circuit and co-emulation verification. New Productivity Improvements Improved Synthesis Using Design Pilot reduces the time to perform logic mapping of a design from RTL to gates, since Design Pilot automates the synthesis process. In addition, Design Pilot now provides a single synthesis pass allowing designers to reduce the time to map the design even further with its export capability. A new bottom-up synthesis option speeds the synthesis time for VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. designers by up to 10x for large designs. In previous releases, Design Pilot only provided top-down synthesis. In addition, Design Pilot can provide incremental synthesis by detecting blocks that have not been successfully synthesized, so a designer can modify the RTL and re-run synthesis only on design blocks that failed. Improved Scripting If a designer maps a design using Design Pilot and then changes the RTL, the designer can simply re-run Design Pilot in script mode, since it records all Graphical User Interface graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to (GUI (Graphical User Interface) A graphics-based user interface that incorporates movable windows, icons and a mouse. The ability to resize application windows and change style and size of fonts are the significant advantages of a GUI vs. a character-based interface. ) operations into a scripted replay file. Interactive Partitioning Design Pilot allows a designer to choose between an automatic partitioning process and an interactive partitioning process. Interactive partitioning visually aids in grouping blocks into System Explorer's programmable logic devices. Design Pilot Benefits Debugging Design Pilot automates the RTL design mapping process and allows users to focus on verifying and debugging designs at the RT-level. It automates the set-up of RTL designs for Aptix's System Explorer and organizes and controls the flow of data between the various emulation preparation steps, making emulation set up easier and shortening the time-to-in-circuit operation. Design Pilot provides access to 4,000 probes to simultaneously observe and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. the internal signals of RTL designs. Since Design Pilot keeps a record of the logical signal translations that occur during synthesis, designers are able to probe at the RT-level. When a designer wants to probe a signal in hardware by specifying the signal at the RT-level, Aptix's Design Pilot and System Explorer automatically decipher the logical to physical translations and present the RTL signals of interest on a logic analyzer (1) A device that monitors computer performance by timing various segments of the running programs. The total running time and the time spent in selected program modules is displayed in order to isolate the least efficient code. or an industry-standard waveform tool. Faster Time-to-Emulation Design Pilot improves the time-to-emulation for RTL designs from weeks to days. Without Design Pilot, a designer is faced with the task of mapping a design written in RTL into multiple programmable logic devices on the System Explorer. Since Design Pilot encapsulates popular synthesis tools and a hierarchical partitioner, it increases engineering productivity by employing Aptix's unique block-based prototyping methodology where each RTL block within a complex design is mapped and verified against its testbench as an independent circuit. "This approach reduces the time to achieve full design in-circuit emulation because the design mapping is done in parallel with the RTL design creation and simulation process," said Raj Mathur Raj Mathur is a board member of the Open Source Initiative. He was elected to the board in April 2007. , Design Pilot Product Manager at Aptix. About System Explorer System Explorer from Aptix uses the latest programmable logic technology and is an emulation platform for the verification, integration and validation of intellectual property and software in SoC designs. Multi-MHz operating speed The operating speed of a road is the speed at which motor vehicles generally operate on that road. The precise definition of "operating speed", however, is open to debate. enables near real-time, in-system verification. Co-simulation interfaces link to popular simulators. The small form factor and affordable cost allow emulation to be applied in ways that were previously impossible. Price and Availability Design Pilot is available today for Solaris workstations. Its price starts at $100,000 (USD USD In currencies, this is the abbreviation for the U.S. Dollar. Notes: The currency market, also known as the Foreign Exchange market, is the largest financial market in the world, with a daily average volume of over US $1 trillion. ) and depends on the configuration, options and use model. Designs created with earlier versions of Design Pilot can be converted using a conversion utility. Customers with previous versions of Design Pilot, who are on maintenance, can receive upgrades. About Aptix Aptix Corporation's products are used to verify, integrate and validate systems and SoC designs prior to integrated circuit and board tape-out and fabrication fabrication (fab´rikā´sh  n),n the construction or making of a restoration. . Visit Aptix on the Web at http://www.aptix.com. Notes: ------------------ Flow graphic available on request Acronyms ASIC: Application Specific IC FPGA: Field Programmable Gate Array HDL: Hardware Description Language IC: Integrated Circuit SoC: System on Chip RTL: Register Transfer (RT-level) VHDL: VHSIC (Very High-Speed IC) HDL Note to Editors: Aptix is a registered trademark of Aptix Corporation. Design Pilot and System Explorer are trademarks of Aptix Corporation. All other registered trademarks or trademarks are property of their respective owners. |
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