Aptix Announces System-on-chip Design Mapping Tool for Rapid System Emulation; New Interactive Software Simplifies the Emulation Process, Increases Predictability of Results.

Business Editors and Technology Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 24, 2000

Aptix Corporation today announced an interactive emulation software environment enabling fast, efficient and predictable creation of prototypes for system-on-chip (SOC) devices directly from RTL designs.

Unlike any tool available today, the environment is unique in its ability to run directly from register transfer-level (RTL) design information and ensure 100% Synopsys-compliant RTL compilation.

The environment, Expedition(TM) emulation software, uses a &uot;consultant in a box&uot; approach that frees users to focus on verifying and debugging SOC designs. The tools automate the set-up of complex electronic circuits for Aptix's popular System Explorer(TM) prototyping tools. As a user-friendly environment, the software organizes and controls the flow of data between the various emulation preparation steps, making emulation easier and shortening the time-to-in-circuit operation.

The software is built around proven technology deployed by Aptix's prototyping services arm for its customers. The package is a front-end tool for Aptix's System Explorer reconfigurable prototyping tools, which map RTL design descriptions to FPGA logic netlists by incorporating logic synthesis and hierarchical partitioning functions within an intuitive, wizard-like graphical user environment.

&uot;In addition to significantly reducing time-to-emulation, Aptix's Expedition software and the wizard-like guide-mode interface help customers to get new design teams up to speed quickly, resulting in significant productivity gains,&uot; said Amr Mohsen, president and CEO of Aptix.

The Expedition package encapsulates Synopsys' FPGA Compiler II(TM) software and a hierarchical partitioner. Expedition software increases the productivity of engineers employing Aptix's unique block-based prototyping methodology where each RTL block within a complex design is mapped and verified against its test bench as an independent circuit. This approach reduces the time to achieve full design in-circuit emulation, because the design mapping is done in parallel with the hardware RTL design creation and simulation process.

The resulting reconfigurable prototype of the design is used to integrate all design blocks and accelerate software integration and debugging. By identifying design problems early in the design cycle, customers have the flexibility to address problems in the most effective manner. This is a welcome proposition to engineers who previously have been forced to implement sub-optimal fixes in the form of software workarounds late in the development process.

Expedition is a complete software environment. The primary elements are as follows:

-- Verilog and VHDL parsers and syntax checkers

-- Design-for-Prototyping checkers that examine the design before

and after synthesis to assure FPGA logic and physical mapping

compatibility with the targeted FPGAs

-- Synopsys' FPGA Compiler II software ensures users that circuits

they prototype and verify in the System Explorer environment will

be equivalent to ASIC designs created by Synopsys' Design

Compiler(TM) tool

-- Hierarchical partitioning software that analyzes the user's

netlist top-down to automatically group blocks within the

hierarchy, achieving fast, flexible implementation in multiple

FPGAs. Feedback in graphical form of the FPGA resource

utilization provides guidance for users to interactively optimize

the FPGA mapping for speed and density.

-- Automated set-up of the Module Verification Platform(TM)

(MVP(TM)) co-emulation interface for linking the prototype

hardware to the customers' simulation software environment

-- Memory compiler for automated development of user-defined memory

About Aptix Corporation

Aptix Corporation's products are used to verify system and system-on-chip (SOC) designs prior to integrated circuit (IC) and board tape-out and fabrication. Aptix's products utilize the block-based verification methodology, which provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This methodology shortens the net prototype creation time to achieve real-world operation of the prototype to the few days required to map and verify the last RTL block designed. Debugging designs becomes simple because the mapping process is both under the user's interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.

The company is privately held and is headquartered at 2880 North First Street, San Jose, Calif. 95134. Telephone [phone], Fax [phone]. Visit Aptix on the Web at: http://www.aptix.com.

System Explorer, Expedition, Module Verification Platform, MVP and Explorer are trademarks of Aptix Corporation. FPGA Compiler II and Design Compiler are trademarks of Synopsys Inc.