Aptix Adds VHDL Simulator Support to Module Verification Platform; Support of HP Computing Platforms Now Available.

Business/High Tech Editors

SAN JOSE, Calif.--(BUSINESS WIRE)--April 17, 2000

Aptix Corporation today announced that it has released a new version of the Module Verification Platform(TM) (MVP(TM)) for regression test acceleration and co-emulation.

This release, MVP 2.1, adds support for popular VHDL simulators. The MVP high-speed data link has also been qualified for the new HP VISUALIZE C3000 Unix workstations, in addition to currently supported Sun Microsystems workstations. These additions give Aptix users complete flexibility in their simulation language (VHDL or Verilog) and operating environments.

MVP provides the ability to drive test benches through individual prototyped design blocks or the entire prototyped system. Interfaces to popular VHDL simulators allow the running of test benches in two ways. The first way is from the simulator environment. Second, a user can interface using the prototyping system to emulate a block of a design being simulated in a co-simulation mode with other design blocks modeled in RTL or even as C models. MVP is included with the new Aptix's SoC Explorer 2000(TM) emulation system (System Explorer(TM) MP4CF) and can be added as an option to the System Explorer MP3C.

MVP consists of a complete hardware and software solution enabling a high-speed link between the simulation environment and target hardware on the Aptix interfaces. Vector depth is limited only by the storage capacity of the computer. Co-emulation through the VH-PI interface is available for the new Scirocco simulator from Synopsys, Cadence NC-VHDL, ModelSim from Model Technology and VSS from Synopsys. This new release of MVP also adds a direct co-emulation interface to Cadence's Cierto SPW, used by many of Aptix's wireless customers, and a new C-API is also available.

The MVP can run in either the vector debug or mixed level co-emulation mode. In the vector debug mode, the MVP drives vectors and compares the output with the expected results, independent of a simulator. The recently announced inclusion of the VirSim(TM) waveform analysis tool in the Explorer 2000(TM) software allows easy selection of data captured to be analyzed by dragging and dropping signals from the RTL source code tree to the waveform viewing window. Automatic generation of system clocking is allowed in MVP and bi-directional signals are supported. In co-emulation mode, users can model their designs in the Aptix system while their test bench is running from their chosen simulator.

The unique advantage to customers of Aptix's proprietary block-based prototyping methodology is that designs can be prototyped in Aptix's System Explorer as each block is completed at the RTL level. This permits incremental verification of the block mapping and validation of the design hardware and software. Since the prototype is created as the design progresses, full prototype real-world environment testing can be done as soon as the last RTL block is mapped into the prototyping system and its correctness verified. This contrasts with "mainframe" ASIC emulation systems that require completion of ASIC designs before the mapping process can begin and that system boards designed and manufactured before real-world testing is possible.

MVP Release 2.1 begins shipping in the second quarter of 2000.

About Aptix Corporation

Aptix Corporation's products are used to verify system and system-on-chip (SoC) designs prior to integrated circuit (IC) and board tape-out and fabrication. Aptix's products utilize a proprietary block-based verification methodology, which provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This methodology shortens the net prototype creation time to achieve real-world operation of the prototype to the few days required to map and verify the last RTL block designed. Debugging designs becomes simple because the mapping process is both under the users interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.

The company is privately held and is headquartered at 2880 North First Street, San Jose, Calif. 95134. Telephone [phone], Fax [phone]. Visit Aptix on the Web at: http://www.aptix.com

MVP, Module Verification Platform, System Explorer, SoC Explorer 2000, and Explorer 2000 are trademarks of Aptix Corporation. VirSim is a trademark of Summit Design.