Applied Materials Announces Industry's First CVD TiSiN Process on New Integrated Barrier/Seed System for Sub-0.1 Micron Copper Chip Development.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 22, 2001

Endura(R) Electra Cu(R) Integrated Barrier/Seed System Combines

CVD(1) Barrier Process with PVD(1) Cu Seed Process on Company's

Benchmark Platform to Enable Future Copper/Ultra-Low k Designs

Applied Materials, Inc. continues its leadership in copper technology with the introduction of the industry's first CVD TiSiN (titanium silicon nitride) barrier process. Combined with the company's established SIP(TM) PVD Cu seed chamber on the new Endura(R) Electra Cu(R) Integrated Barrier/Seed system, the CVD TiSiN process provides customers with an optimized single system solution for the development of future sub-0.1 micron copper/ultra-low k chip designs on 200mm or 300mm wafers.

"In production manufacturing, PVD is expected to continue to be the preferred process for both barrier and seed layer deposition for the next several device generations due to its low cost, high-throughput and simplified process and hardware," said Dr. Fusen Chen, vice president and group general manager of Applied Materials' Cu, PVD & Integrated Systems and Modules Business Group. "And we expect Applied Materials' landmark Endura Electra Cu Barrier/Seed system to continue to be the production tool of choice for this application.

"As a technology leader, Applied Materials developed the new Endura Electra Cu Integrated Barrier/Seed system to allow customers to extend and develop their chip designs with sub-nanometer technologies, including the use of very advanced ultra-low k materials. Multiple systems with the CVD TiSiN chambers have already been shipped to customers in the U.S. and Asia, where they are being used for the development of both logic and memory devices."

Applied Materials' new CVD TiSiN process is the key to the advanced capabilities of the Endura Electra Cu Integrated Barrier/Seed system. Targeted to provide good step coverage on the typically rough or uneven interconnect sidewalls presented by the new porous ultra-low k (k less than 2.2) dielectric materials being studied, the low temperature CVD TiSiN process enables greater than 85 percent sidewall and bottom coverage in small, high aspect ratio features. Providing a thin, conformal film, the CVD TiSiN process allows high copper conductivity of the interconnect structure, yet provides an excellent barrier to prevent copper diffusion into other areas of the device.

The CVD TiSiN process, which uses Applied Materials' production-proven TxZ(TM) chamber hardware, has been fully integrated with the company's SIP(TM) PVD copper seed layer processes on the Endura Electra Cu Integrated Barrier/Seed system. The system has also been integrated with the company's Electra Cu ECP copper fill and Mirra Mesa(TM) CMP processes for an optimized metallization sequence. Applied Materials modeled the Integrated Barrier/Seed system after its award-winning Endura Integrated Liner/Barrier product for aluminum interconnect fabrication.

The market for Barrier/Seed layer PVD systems was estimated at $763 million by Dataquest for the calendar year 2000, with projected growth to $1.36 billion by 2005. The transition to CVD technology for the barrier layer film is not shown in Dataquest's projections.

To ensure future extendibility of the company's installed base of Endura Electra Cu Barrier/Seed systems, which are used by virtually every chipmaker engaged in copper development or production worldwide, customers can easily upgrade existing systems with the CVD TiSiN chamber.

Applied Materials (Nasdaq:AMAT), the largest supplier of products and services to the global semiconductor industry, is one of the world's leading information infrastructure providers. Applied Materials' web site is http://www.appliedmaterials.com.

(1) Acronyms spelled out at end of text.

(1) CVD: chemical vapor deposition PVD: physical vapor deposition SIP: self-ionized plasma ECP: electrochemical plating CMP: chemical mechanical polishing