Apache Announces RedHawk-LP, a Dynamic Power Integrity Solution for Low Power and Leakage Control Designs.MOUNTAIN VIEW, Calif. -- Apache Apache (əpăch`ē), Native North Americans of the Southwest composed of six culturally related groups. They speak a language that has various dialects and belongs to the Athabascan branch of the Nadene linguistic stock (see Native American Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced RedHawk-LP, a dynamic power integrity solution for analysis and optimization of low power and leakage LEAKAGE. The waste which has taken place in liquids, by their escaping out of the casks or vessels in which they were kept. By the act of March 2, 1799, s. 59, 1 Story's L. U. S, 625, it is provided that there be an allowance of two per cent for leakage, on the quantity which shall appear control designs. RedHawk-LP provides the most accurate and complete power solutions for designs utilizing various low power and leakage management techniques, including power-gating with full-chip ramp-up analysis and switch optimization, and multiple-Vdd/Vss cells with multiple voltage domains. RedHawk-LP expands Apache's silicon-proven full-chip dynamic power integrity product portfolio by delivering the most advanced power analysis and design optimization See automatic design optimization. solution for low power SoCs. Leakage: A Dominant Source of Overall Power At 90nm and below, leakage will start to dominate the chips overall power. Engineers are employing techniques such as power-gating or multi-threshold-CMOS (MTCMOS) switches to control the amount of leakage in their designs. RedHawk-LP's Spice-accurate MTCMOS switch modeling, full-chip capacity and performance, and true-transient simulation engine enable designers to accurately analyze the chip's non-linear behavior during ramp-up (sleep to active), including how the current surge during ramp-up impacts the timing of surrounding logic. RedHawk-LP supports mixed-mode analysis where designers can analyze how simultaneous "ON," "OFF" and "power-up" states impact the chip's overall power and timing. To guide the designers in identifying potential design issues, RedHawk-LP provides various visualization Using the computer to convert data into picture form. The most basic visualization is that of turning transaction data and summary information into charts and graphs. Visualization is used in computer-aided design (CAD) to render screen images into 3D models that can be viewed from all tools such as current profile, Vdd/Vss waveforms and full-chip movie playback. By using RedHawk-LP's movie mode, designers are able to view the instance-based voltages over the micro- to milli-seconds of time required for a complete ramp-up operation. In addition to identifying potential design issues, RedHawk-LP with FAO FAO, n See Food and Agriculture Organization. (fix and optimization) allows engineers to optimize their designs to meet ramp-up timing and voltage-drop requirements. With RedHawk-LP, designers can determine the optimal size, number and location of the MTCMOS switches to control leakage, while maintaining the integrity of the design. RedHawk-LP allows designers to determine the best strategy for turn-on timing of the switches to meet the chip's performance and power requirements. RedHawk-LP also provides the ability to automatically remove ineffective decaps and switches, thus reducing excessive leakage caused by devices that do not contribute to the overall power integrity of the chip. Instance-based Multi-Vdd/Vss and Multiple Voltage Domains RedHawk-LP supports cells with multiple Vdd and Vss that are typically found in level-shifters, retention flip-flops and memories for multi-voltage domain designs. This common low power design technique enables engineers to control and trade off power consumption and performance. RedHawk-LP enables designers to analyze the current profile and power distribution for each of the voltage domains by concurrently simulating multiple voltage islands within a full-chip context, thus delivering more accurate and realistic results. Complete Low Power Design Integrity "Apache is a leader in dynamic power integrity with 100s of successful power tape-outs by over 40 customers worldwide," said Andrew Yang yang (yang) [Chinese] in Chinese philosophy, the active, positive, masculine principle that is complementary to yin; see yin, under principle. , CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Apache. "As designs move beyond 90nm, leakage management will become a key concern for designers and Apache is addressing this need by delivering a complete low power solution that enables silicon success and increased yield." Pricing and Availability RedHawk-LP is immediately available for customer use. Annual license pricing starts at $275,000. Existing RedHawk-EV customers can add the low power analysis and optimization capabilities to their current licenses. It is licensed on Linux, Sun Solaris and HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. . About Apache Design Solutions Apache is an EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design -- such as power, signal, package/system IO, substrate The base layer of a structure such as a chip, multichip module (MCM), printed circuit board or disk platter. Silicon is the most widely used substrate for chips. Fiberglass (FR4) is mostly used for printed circuit boards, and ceramic is used for MCMs. and temperature -- Apache's silicon signoff platform enables designers of leading networking, wireless, communication, consumer and semiconductor companies to detect, fix and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral platform enables designers to adopt any industry-standard physical design flow and is certified See certification. by TSMC's 5.0 and 6.0 Reference Flow (NYSE NYSE See: New York Stock Exchange :TSM TSM Tivoli Storage Manager TSM Transportation System Management TSM Taiwan Semiconductor Manufacturing (stock symbol) TSM Taiwan Semiconductor Manufacturing Co. Ltd. ). Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies. For more information, visit www.apache-da.com. Apache Design Solutions, NSPICE, RedHawk, PsiWinder and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. |
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