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Apache's Latest Release of RedHawk-EV Delivers Higher Performance and Capacity.


MOUNTAIN VIEW, Calif. -- Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced that their latest release of RedHawk-EV delivers at least 2X faster runtime performance and 40% less memory utilization for full-chip dynamic power integrity compared to the previous released version.

The speedup and capacity improvements increase based on the size and complexity of the design. In a recent tapeout support, the dynamic simulation run-time was reduced from 14 hours 30mins to 6 hours 38mins on a 65nm design with 8M gates. On a larger design with 110M gates, RedHawk-EV version 5.3 delivered an even more significant runtime speedup with a total run-time reduction from 58 hours to that of 12 hours running on a 64-bit machine. This was a highly complex design whose analysis included a RDL RDL - Requirements and Development Language.

["RDL: A Language for Software Development", H.C. Heacox, SIGPLAN Notices 14(9):71-79 (Sep 1979)].
 (Re-Distribution Layer) with complex power routings and with on-chip memories fully modeled down to the lowest level of metal.

"As design size and complexity increases, the tools used by customers to validate their designs need to keep pace with their demands," said Dian Yang, vice president of product management at Apache. "In spite of our significant competitive lead in runtime and capacity, Apache continues to enhance our products and technologies to meet the needs of our customers' most challenging designs."

"The latest enhancements in performance and memory are obtained from upgrades of our core physical database, extraction engine, and simulation kernel with no impact on waveform accuracy," said Andrew Yang, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  of Apache Design Solutions. "The new version improves customers' productivity by significantly reducing the overall turnaround time of deploying full-chip dynamic solutions to SoC designs at 65nm and below."

Apache will be demonstrating RedHawk-EV, along with their complete power integrity and noise management solutions, at the upcoming Design Automation Conference (DAC See D/A converter and discretionary access control.

DAC - Digital to Analog Converter
) in San Francisco, California “San Francisco” redirects here. For other uses, see San Francisco (disambiguation).

The City and County of San Francisco (EN IPA: [sænfrənˈsɪskoʊ] 
, July 24 - 27, in booth #1906.

Availability

RedHawk-EV version 5.3 is immediately available for customer use. All existing RedHawk-EV customers will automatically receive version 5.3 as part of their maintenance.

About RedHawk

RedHawk is a full-chip Vectorless Dynamic(TM) physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC's 5.0 and 6.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO See single sign-on and CSO.

SSO - single sign-on
) for core, memory, clock, and I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
, as well as effects of on-chip inductance, package RLC RLC Residual lung capacity , and decoupling Decoupling

The occurrence of returns on asset classes diverging from their normal pattern of correlation.

Notes:
Take for example stock and corporate bond returns, which normally rise and fall together.
 capacitance. RedHawk delivers transistor-level accuracy with cell-based capacity, performance, and ease-of-use.

With RedHawk designers can identify dynamic "hot spots," examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. RedHawk enables designers to reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, MTCMOS (power-gating), multiple voltage domains, and multiple threshold transistors.

About Apache Design Solutions

Apache is an EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design--such as power, signal, package / system IO, substrate, and temperature--Apache's silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral platform enables designers to adopt any industry-standard physical design flow and is certified by TSMC's 5.0 and 6.0 Reference Flow (NYSE NYSE

See: New York Stock Exchange
:TSM TSM Tivoli Storage Manager
TSM Transportation System Management
TSM Taiwan Semiconductor Manufacturing (stock symbol)
TSM Taiwan Semiconductor Manufacturing Co. Ltd.
).

Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies. For more information, visit www.apache-da.com.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.
COPYRIGHT 2006 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:Jun 30, 2006
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