Anova Launched to Tackle Process and Design Variations; Veteran EDA Startup Team Creates Unified Variation Model to Analyze Variation and Provide Solutions for 65nm and Below.

SANTA CLARA, Calif. -- An experienced team of design-tool innovators has formed Anova Solutions Inc. and created a new EDA tool suite to analyze process and design variations to maximize yield and performance in 65nm and below designs. Working with Fujitsu Limited, the company has developed the Anova Suite(TM) centered on a unified variation model generator reducing design uncertainties and unnecessary margins to maximize high-end silicon potential. The analysis suite provides enormous value in making effective decisions in design capabilities when moving to a smaller process or if the move is going to be effective in improving a design's performance.

"Our design collaboration with Anova solutions has shown tremendous results and the first variation-aware timing model and analysis technologies from Anova are being included in Fujitsu's 65nm design flow," said Satoshi Andou, general manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu Limited. "We will continue our partnership with Anova to establish the variation model and analysis technologies in our future design flow to maximize 65nm process silicon potential values."

"From our team's experience in developing the industry-standard ECSM model, we believe ECSM or CCS, which targets timing nonlinerarities and signal integrity accuracy, is inadequate. The next generation of signoff needs to be variation aware," said Jun Li, founder, CEO and president of Anova Solutions. "The invisibilities in the smaller design processes make it almost impossible to know if your design will function at 65nm, even if you do reduce design size and improve performance. "As a result, designers have to include enormous and unnecessary margins in a design, reducing functionality and increasing the amount of time it takes to produce a chip. Our analysis suite can effectively eliminate that uncertainty and decrease decision-making time by multiple orders of magnitude."

The Anova Suite's unified variation model captures the process and transistor device variation, describes the variation in timing and power libraries and provides the variation constraints to the design, including correlations, possibilities and best/worst cases. Using the suite, designers can reduce the margin to maximize the potential of a leading edge process; reduce turn-around time by limiting corners in the lithography; insert flexibility in the variation signoff; and accelerate the product yield ramp by linking the variation with process-critical parameters.

Anova Solutions delivered the layout based variation analysis engine to Fujitsu in December 2005. The stochastic analysis process (SAP) engine for model generation (patent pending) was delivered in April of 2006. Between now and 2008, Anova Solutions will add design variation analysis and optimization. Later this year, they will be establishing alliances with OPC, lithography and DFM leaders under those results.

About Anova Solutions

Anova Solutions was founded in 2004 by a team of engineers that invented the industry-standard Effective Current Source Model (ECSM), popularized by Cadence Design. The team, including Jun Li, has more than 50 years experience in EDA tool development. The board of directors includes Li; Ping Chao, formerly senior executive vice president at Cadence; and Hiroyoshi Usuda, formerly CFO of Innotech. Anova Solutions is financed by a combination of private and corporate investment, and a current revenue stream. For more information, go to www.anova-solutions.com