Analogix Unveils First High-Speed Backplane SerDes ICs With Adaptive DSP-Based Noise Cancellation.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--April 5, 2004

Advanced Analog+DSP Architecture Enables FR-4 Backplane

Upgrades to 6.25G; Later Products Will Facilitate System

Interconnect over Low-Cost Copper

Analogix Semiconductor has introduced the first high-speed physical-layer transceivers that incorporate digital signal processing (DSP) techniques to eliminate the signal integrity ("noise") problems associated with 5- and 10-gigabit-per-second data transmission over backplanes and copper media.

The D-PHY family of SerDes ICs is based on a new architecture that combines Analogix's WideEye(TM) technology - a set of adaptive DSP-based noise-cancellation techniques - with advanced analog signal conditioning. Unlike analog-only solutions, which simply mask detrimental signal effects such as crosstalk and reflections, the D-PHY family actually removes these effects, ensuring maximum signal integrity.

With noise problems eliminated over standard FR-4 backplanes and very-short-reach (VSR) system-to-system copper interconnects, system designers can:

-- upgrade existing backplane systems with four-fold performance;

-- design new, higher-speed systems with low-cost connectors and

easily manufactured FR-4 materials rather than far more

complex and expensive materials; or

-- replace fiber-optic inter-system connections with much

lower-cost standard unshielded twisted pair (UTP) or

InfiniBand copper cable at distances of up to 50 meters.

The D-PHY family is designed for use in enterprise switches and routers, carrier-class transport equipment (including optical switches and cross-connects), Fibre Channel and IP-based storage systems, and high-end servers.

The first D-PHY products, D-PHY 5G backplane transceivers, are being announced today. A 10-Gbps serial backplane transceiver family and a 10-Gbps serial interconnect over copper IC family will be introduced later this year.

Analog-only Approaches Can't Handle Noise Issues at High Speeds

Ted Rado, vice president of marketing at Analogix, said, "The ubiquitous copper-based FR-4 backplanes in today's systems were designed when speeds of 5 Gbps and above weren't even imagined. Now designers of switches, servers, storage arrays and the like want more performance, but they want to get it by upgrading, not replacing, their existing systems. As vendors try to design new high-speed cards that fit into old FR-4 backplanes and interoperate with existing cards, they face major noise issues that analog techniques can't handle - not just signal attenuation but crosstalk and reflections. Since the backplane itself has a fixed number of traces, the burden is on the silicon to deal with the increased noise while pushing more performance through those traces.

"The same issues surface in system-to-system interconnect, where, even at distances of under 50 meters, copper media have severe noise issues at speeds over 1 Gbps," Rado added. "Thus far, expensive, power-hungry fiber solutions have been the only choice."

D-PHY Architecture: Adaptive DSP Signal Conditioning

Joins Advanced Analog Techniques

Analogix's solution is the D-PHY architecture, an advanced analog/DSP-based approach that maximizes signal-conditioning flexibility. Like traditional analog-based SerDes technology at 3.125 Gbps and below, D-PHY devices offer standard transmitter-programmable pre-emphasis and swing control. Up to now, companies targeting speeds beyond 3.125 Gbps have incorporated more advanced analog receive-based equalization, typically in the form of Decision Feedback Equalizers (DFEs). The D-PHY architecture's two chief elements - one analog, one DSP - offer significant advantages over such approaches:

-- Multi-stage continuous-time linear equalizer. This advanced

analog signal-conditioning element has the benefits of

DFE-based solutions with half the power consumption and die

area. It also scales more effectively to 10 Gbps because its

feedback loop does not occur at the maximum frequency.

-- WideEye technology. A set of DSP-based adaptive

signal-conditioning elements, WideEye includes adaptive

equalization, adaptive reflection and crosstalk cancellation,

and error correction coding. These techniques, unprecedented

in backplane devices, maximize system vendors' design margins

and flexibility in both upgraded and new designs. To address

power concerns implicit in DSP technology, D-PHY chips offer a

unique PowerSelect option, which lets users turn off

individual WideEye functions for high-quality channels; this

brings typical power consumption down to 2.9 watts or less.

D-PHY 5G Product: 6.25G Serial Performance on an FR-4 Backplane

The D-PHY 5G backplane transceivers offer 1.25- to 6.25-Gbps serial transmission across up to 60 inches of standard FR-4 backplane material and two connectors. Two versions are available. The D-PHY 4x5G quad transceiver, with four high-speed links, provides up to 25 Gbps full-duplex transmission. The D-PHY 2x5G dual transceiver, with two links, performs at up to 12.5 Gbps. NRZ binary encoding on both devices ensures backward-compatibility with lower-speed SerDes transceivers. All D-PHY devices are compliant with the Optical Internetworking Forum's Common Electrical I/O (CEI) 6G+ specification.

Each D-PHY device also has eight low-speed (800 Mbps-3.125 Gbps) SerDes links. Flexibility is increased by three multiplexing options: 1:1, 2:1 and 4:1; a unique legacy mode available with 1:1 multiplexing detects connection with another SerDes device (e.g., a XAUI transceiver), allowing new cards to interoperate with existing ones. Comprehensive built-in self-test (BIST) functionality includes on-chip PRBS generators and error checkers as well as low- and high-speed loop-back paths for independent testing of all chip elements. D-PHY devices also offer real-time bit error rate (BER) monitoring capabilities by polling MDIO- or I2C-controlled WideEye DSP registers.

D-PHY 5G Pricing and Availability

The D-PHY 5G backplane transceiver is sampling now and will be available in production volumes in June. High-volume prices are $49 each for D-PHY 4x5G devices and $28 each for D-PHY 2x5G devices. The devices come in JEDEC-standard 260-pin HSBGA (Heat Slug Ball Grid Array) packages.

About Analogix Semiconductor

Analogix Semiconductor, Inc., founded in March 2002, manufactures high-performance analog mixed-signal semiconductors. Its initial products are high-speed physical-layer transceivers (SerDes) that extend the performance and reach of backplane and system-to-system interconnect over copper media. Analogix products combine advanced analog with digital signal processing (DSP) techniques to offer interconnect speeds of up to 10Gbps. Target customers include enterprise and carrier networking, storage and server system vendors.

Analogix is based in Santa Clara, Calif., with development offices in Beijing, China. The privately-held company, which has 40 employees, has raised $10 million from Woodside Fund, Doll Capital Management and IDG Technology Venture Investment. For more information, visit http://www.analogix.com.

Note to Editors: In "I2C" the 2 is superscript.