An open architecture approach to buried passive components: a now expired patent for capacitive power/ground planes in a circuit board could mean that, for thin power ground capacitive layer applications, restrictions are off.

Many applications available to OEM manufacturers for capacitive layer technology, both separately and in combination with resistor technologies, are no longer restricted because the patents that originally described the technology have expired or the technique may be used without restriction.

A planar sandwich capacitor (FIGURE 1) develops a distributed capacitance based on the formula

C = A[epsilon]D/t,

where C is capacitance in picofarads, A is area in square inches, [epsilon] dielectric constant of the insulator, D is a conversion factor (225) and t is the dielectric insulator thickness in mils.

[FIGURE 1 OMITTED]

TABLE 1 lists some general trends of the planar capacitor technology. All the technologies described operate on the formula above for simple plate capacitors.

The most senior patent in the field, Leary, is very important and is discussed in detail later. Many patents and methods exist that are not listed on the chart. As can be seen in TABLE 1, development of planar capacitive PCBs began in the mid 1980s. The order of that development is shown in TABLE 2.

Some of the significant capacitive plane type patents, such as a simple plane as shown by Leary, have expired. Leary fully describes the use of capacitive power/ground planes in a circuit board and uses the same calculation for the amount of capacitance developed as all the other planar capacitors in this field. Many applications may use this type of thin power ground capacitive layer without restriction. All thin power ground sandwiches that are thin because of overall thickness requirements fall into this category and many other capacitive planes may fit this definition based on their design. This type of layer is the primary component of an open architecture approach to embedded passive components. By using the Leary type plane with a well-known planar resistor technology such as the Omega Ply material, a complete embedded passive PCB may be fabricated without any special license or cost other than the special materials. This method is cited in this paper as an open architecture model to which other unrestricted technologies may be added.

Leary Explained

Leary (4,494,172) discloses a capacitive "multilayer panel board" (col. 1, 5-10 and 17-26) [Ed.--The parenthetical references are to specific paragraphs in Leary. Figures 4 and 5, as referenced in subsequent paragraphs, are also part of the Leary patent.] The panel board's conductive layers are imaged, printed and etched to form a series of paired power and ground columns of through-hole connectors (col. 6, 24-46).

The "multilayer panel board" is formed by laminating layers to a glass--epoxy core stock (faced on both sides with copper foil) (col. 6, 24-34). In Figures 4 and 5, the voltage plate (18) separated by glass epoxy layer (24) from the ground plate (16) is a capacitor laminate.

Having "mounted electronic components" (col. 1, 65-68).

The glass epoxy core stock faced on both sides by copper foil (laminate) constitutes the base for a multi-layered laminate (col. 6, 24-34).

The epoxy layer having a preferred thickness of 0.005"-0.009" between the copper foil power/ground plates provides a "large distributed capacitance" for the mounted electronic components (col. 4, 6-8; col. 6, 24-34; Figures 4 and 5) where the first sheet of conductive material forms a voltage plate (18) and the second sheet of conductive material forms a ground plate. (16)

Figures 4 and 5 show a multiple capacitor laminate structure. The capacitor (14) + (22) + (16) is in spaced apart relation to the capacitor structure (18) + (26) + (20).

In Figure 4, the through-hole (28) the power plate (14) of capacitor structure (14), (22) and (16) is wired in parallel to the power plate (18) of capacitor structure (18), (26) and (20). In Figure 5, the ground plates are also wired for through-hole (30) connection with surface devices.

Figure 4, where epoxy layers (24), (26) are "thin enough" to establish "a large distributed capacitance" of at least 0.02 microfarads between the voltage plate (18) and ground plates (16), (20) (col. 4, 5-10).

The capacitive layer in the board "inhibits switching signals from causing voltage spikes in the power lines" from the mounted high-speed switching ICs (col. 2, 41-45).

The capacitance provided by the capacitive layer in the board eliminates the requirement of including "many discrete isolation capacitors" (col. 2, 41-45).

While Leary discusses a thicker layer than many of the future technologies, it fully discloses the concept of a thin plane capacitive power/ground plane and the types of values that may be calculated for the distributed capacitance of the planes.

It is the conclusion of this paper that technologies, such as the capacitive planes described in Leary, are available to manufacturers who use simple capacitive planes to create inexpensive capacitive PCBs. Of course, other high technology capacitive planes are available; some are restricted by patent and license. By combining the simplest of these technologies it is now possible to practice these technologies without special license or restrictions. This may prove to be a very large cost savings to those companies that use large volumes of these types of materials.

This paper is adapted from a presentation at the IPC Fall Meeting in September 2003 and is reprinted with permission of the author.

TABLE 1. Sample Chart of Planar Capacitance Technologies

TYPE                DIELECTRIC
                    THICKNESS

Capacitive planes   [approximately equal to] 0.005-0.009"
Layered Ink         [approximately equal to] 0.001"
Capacitive planes   [approximately equal to] 0.001-0.005"
Capacitive planes   [approximately equal to] 0.0015"
Capacitive planes   [approximately equal to] 0.002"
Capacitive planes   [approximately equal to] 0.002"
Capacitive planes   > 0.002"
Capacitive planes   [approximately equal to] 0.002"
Capacitive planes   [approximately equal to] 0-0.0005"
Capacitive planes   [approximately equal to] 0.0005"
Capacitive planes   [approximately equal to] 0-0.0003"
Capacitive planes   [approximately equal to] 0.002-0.004"

TYPE                DIELECTRIC            INVENTOR,
                    MATERIAL              ASSIGNEE

Capacitive planes   Epoxy                 Leary, Mupac
Layered Ink         Polymer               Turek, West-tronic
Capacitive planes   PTFE                  Fischer, WL Gore
Capacitive planes   Epoxy                 Sisler, Unisys
Capacitive planes   Epoxy                 Howard, Sanmina
Capacitive planes   Epoxy BaTI03          Paurus, Sanmina
Capacitive planes   Resin with powder     Ozawa, Murata
Capacitive planes   Resin with additives  Lucas, Sanmina
Capacitive planes   Deposited layers      Hoffarth, IBM
Capacitive planes   Two deposited layers  Frankeny, IBM
Capacitive planes   Polymer               O'Bryan, 3M
Capacitive planes   Polymer               Appelt, IBM

TYPE                UNIQUE ELEMENT                 GRANT      EXPIRE
                                                   DATE       DATE

Capacitive planes   Parallel plane capacitors      1/15/85    1/15/02
Layered Ink         Polymer conductive circuit     10/4/88    10/04/05
Capacitive planes   PTFE dielectric                2/26/91    2/26/08
Capacitive planes   Manufacturing method           4/30/91    4/30/08
Capacitive planes   Use of borrowed capacitance    1/07/92    1/07/09
Capacitive planes   Prefired nanopowder            11/19/92   11/19/09
Capacitive planes   Resin with powder              12/15/92   12/15/09
Capacitive planes   Insitu method of lamination    4/06/92    4/06/09
Capacitive planes   Different dielectric materials 3/25/96    3/25/13
Capacitive planes   Two deposited layers           4/1998       N/A
Capacitive planes   Peel strength                  8/14/01      N/A
Capacitive planes   Two dielectric sheets          4/10/01    11/15/18

TABLE 2. Order of Planar Capacitive PCBs

TYPE OF TECHNOLOGY                                INVENTORS

Planes separated by thin dielectrics              Leary, Turek,
                                                  Fischer, Sisler
Planes operating on the principle                 Howard
of borrowed capacitance
Special dielectric materials including additives  Paurus, Ozawa
Special "insitu" method of manufacture            Lucas
Multiple dielectric layers,                       Hoffarth, Frankeny
including different materials
Ultra-thin high capacitance dielectrics           O'Bryan

TYPE OF TECHNOLOGY                                  FIRST
                                                  INTRODUCED
Planes separated by thin dielectrics                 1985
Planes operating on the principle                    1992
of borrowed capacitance
Special dielectric materials including additives     1992
Special "insitu" method of manufacture               1992
Multiple dielectric layers,                          1996
including different materials
Ultra-thin high capacitance dielectrics              2001

JAMES HOWARD is technical director of WUS Printed Circuit Co. (wus.com.tw). He can be reached at [e-mail].