An integrated approach to designing-in FPGAS: FPGA/PCB integration is time consuming and error-prone. Automating communication between the flows can eliminate the impact of an FPGA I/O design change on the PCB design.

As FPGA architectures have evolved from thousands of gates to millions of gates, FPGA packages have evolved from hundreds to thousands of pins. While the pin pitch on an FPGA package has been constant, the size of the FPGA package, and consequently the pin density on the PCB, has increased significantly. This creates interconnect routing congestion issues and in turn creates the need for (costly) HDI PCBs.

Another complication associated with FPGA device implementations is that the I/O design is fluid. As a result, many PCBs have been re-spun because the PCB and the FPGA design teams did not have the I/O design synchronized. FPGAs are the only devices on a board that contain the flexibility to significantly reduce PCB re-spins, routing congestion and signal layers, while potentially reducing the number of components on the PCB.

Mastering FPGA I/O design within the context of integrated system design (ISD) holds tremendous potential for product design teams. It allows them to reduce time-to-market by minimizing FPGA/PCB design iterations and significantly reducing PCB routing congestion. It also helps to limit PCB re-spin costs due to I/O synchronization issues between the FPGA and PCB design flows. By allowing PCB designers to eliminate signal layers, it will also help to lower PCB manufacturing costs.

The traditional independence of the FPGA and the PCB design teams can still result in an "over the wall" serial approach to FPGA I/O design (FIGURE 1). This involves the following steps:

[FIGURE 1 OMITTED]

* The FPGA designer defines the top-level block of the design, thus establishing the logical signals.

* The FPGA designer locks specific signals (clock signals, specific high-speed signals) during the FPGA synthesis step.

* The FPGA vendor's place and route software automatically assigns the remaining FPGA top-level signals to physical device pins and creates the FPGA device pin map file.

* The FPGA pin mapping is communicated to the PCB design team, where the librarian creates a definition for the FPGA device.

* The PCB designer instantiates the FPGA symbol into the PCB schematic.

* The PCB schematic is driven into the PCB place and route tool.

By necessity, the over-the-wall approach requires at least one additional cycle through the complete FPGA/PCB design flow. This cycle could potentially be eliminated if the FPGA and PCB design teams first collaborated on the FPGA I/O design.

The traditional approach to FPGA/PCB integration is time-consuming and error-prone. Moving the FPGA I/O design data from the FPGA design flow into the PCB design flow (between steps 3 and 4 in Figure 1) is often a manual data re-entry step, opening the door for data entry errors.

To understand the magnitude of the data under discussion, consider the amount of information associated with each pin on the FPGA. There is a logical signal name, physical pin number, pin direction, pin-bank (pin swap group), FPGA device generic pin name and differential signal pin pair.

If the FPGA device has 1,000 pins, the PCB librarian will need to enter 6,000 pieces of data without a single error. Errors in the PCB symbol for an FPGA may result in PCB manufacturing re-spins. If the logical signal name and physical pin number are not synchronized between the FPGA and PCB design flows, the FPGA may not operate on the PCB.

In addition, the representation of the FPGA for the PCB must be actively maintained. In the default FPGA place and route flow, the FPGA I/O design will change. The FPGA place and route flow leverages the I/O assignment freedom" to meet FPGA design timing constraints. An FPGA designer must take additional steps to lock the FPGA I/O design so that it will remain constant as the design evolves.

The physical integration of the FPGA device onto the PCB design is often quite expensive to create and maintain for high pin-count devices. Due to the high integration costs product design teams often lock the FPGA I/O design early in the design process. This helps mitigate the FPGA/PCB integration maintenance costs, but it also completely eliminates the opportunity to optimize the PCB manufacturing costs.

Many design teams lock the FPGA I/O design early in the design process and then find themselves confronted with the need to alter the FPGA I/O design to meet either PCB routing requirements or performance requirements. Unprepared to effectively deal with FPGA I/O change, these design teams often encounter unexpected design delays.

Design Flow Requirements

The first barrier to ISD is often institutional: the management organization of the FPGA and PCB design teams. The traditional FPGA/PCB integration process is serial and does not draw on the expertise of the PCB design team until after an FPGA I/O design has been created. The PCB design team has the total product design vision that will produce critical insight necessary to optimize the FPGA I/O design. Therefore, the FPGA I/O design process must be a collaborative, concurrent design effort shared by the FPGA and PCB designers.

But remember that the PCB design team does not necessarily have the expertise to participate effectively in FPGA I/O design process. A modern FPGA architecture contains programmable I/Os that may support more than 50 different I/O standards. A variety of single-ended and low-voltage differential signal (LVDS) I/O standards typically are available. And while FPGA I/O designs are fluid, they are only flexible up to a point. Modern FPGA architectures group collections of pins together into pin-banks. Pins within a pin-bank share some common characteristics, such as a reference voltage, and are generally swappable. However, pins in different pin-banks may have incompatible I/O standards assigned to them, resulting in a number of situations.

One situation occurs when a PCB designer asks for an FPGA I/O pin change to meet PCB interconnect performance specifications or for board routability. Another situation could occur when an initial pin change creates an I/O standard cohabitation violation, forcing an existing signal to be moved into a new pin-bank. A third appears when relocated signals from the previous situation create an I/O standard cohabitation violation, forcing existing signals to be moved to a new pin-bank (FIGURE 2).

[FIGURE 2 OMITTED]

Obviously, optimizing the FPGA I/O design to meet PCB design requirements would require making the complex FPGA I/O design rules easily accessible to PCB designers. In addition, the assumption must be that the FPGA I/O design will change. Consequently, ensuring synchronization between the FPGA and the PCB design flows is essential.

FPGA architectures have evolved to support LVDS pairs. When an LVDS I/O standard is assigned to a signal in the FPGA device, the FPGA signal will use two pins on the FPGA package. LVDS signals are used primarily for high-speed signals where signal integrity issues are a concern. LVDS signals yield performance benefits for the PCB, but they also impose additional constraints. LVDS trace pairs must:

1 Be matched in length to +/- 10%.

2. Maintain a fixed separation between the differential pair traces across their entire length.

3. Be routed on the same signal layer.

Using too many LVDS I/O standards for FPGA logical signals could create the need to move up to a larger FPGA package with more pins. Not having access to LVDS I/O standards would imply performance limitations that many product design teams would find unacceptable. The ability to easily change from single-pin to dual-pin 110 standards (and back again) gives the entire design team the ability to explore meeting system performance constraints with the least number of LVDS I/O signals (LVDS use increases PCB manufacturing complexity and costs).

Changing the FPGA I/O design from within the FPGA design flow is fairly trivial. A number of available tools offer the FPGA designer the opportunity to create or change the I/O design, including FPGA design entry, design synthesis and place-and-route.

But changing the physical design of the PCB is not so trivial and may prove very expensive. When a logical signal moves across the FPGA, the PCB trace that connects that signal to the rest of the design must be moved. On a complex PCB, the trace that is moved will cause other traces on the PCB to be moved. Again, the need to be able to lock the FPGA I/O design as the complete product design evolves is amplified.

At the moment, most system design teams avoid FPGA I/O design changes, which are viewed as high risks. While this perception is historically accurate, a failure to overcome these challenges has created a situation where fear of I/O change may cause the product design to fail. At a minimum, the fear of I/O change has led to increased PCB manufacturing costs.

The communication between the FPGA and PCB design flow must be completely automated to effectively eliminate the impact of an FPGA I/O design change on the PCB design. That automation must include the ability to create and maintain a representation of the FPGA for the PCB design process.

The basic requirements to significantly improve the complete system design process include:

* Concurrent FPGA and PCB team design of the FPGA I/O.

* Easy PCB designer access to complex FPGA I/O design rules.

* Absolute synchronization of the FPGA I/O design between the FPGA and PCB design flows.

* Complete automation of the creation and maintenance of the FPGA device representation for the PCB design flow.

* Elimination of all phobias regarding FPGA I/O changes.

An ISD approach to routing encompasses both the FPGA and PCB design domains to achieve a "big picture" perspective. Educating a PCB designer on the complex FPGA I/O pin banking rules may prove frustrating for everyone, but building the I/O pin-banking rules into a tool the board designer can use unlocks their insight for the FPGA I/O design process.

Mastering concurrent FPGA and PCB team design of the FPGA I/O and automating the physical integration of the FPGA and PCB design flows allows design teams to use the flexibility of the FPGA I/O to reduce PCB routing congestion. A careful examination of modern FPGA architectures and their usage reveals some interesting facts:

1. Pins within a pin-bank are easily swappable.

2. Signals within a bus in the design are generally assigned to the same pin-bank (to take advantage of easy pin swapping).

3 Pin-banks may not represent the best physical design for a bus of signals in the design (using the same pin-bank may force signals in the bus to cross over one another on the PCB). See FIGURE 3.

[FIGURE 3 OMITTED]

By learning to effectively use multiple pin-banks to physically optimize the FPGA I/O to eliminate crossing signals within buses, it is possible to also reduce the number of signal layers required to manufacture the PCB (FIGURE 4). And just as the communication barriers between PCB design and fabrication have fallen, the organizational barriers between the FPGA and PCB design must fall to achieve product success.

[FIGURE 4 OMITTED]

DAVE BRADY is a product marketing manager for Mentor Graphics' FPGA tools (mentor.com). He can be reached at [e-mail].