Amphion's JPEG Accelerator Cores Smash Megapixel Performance Barrier for Personal Imaging and Consumer Video Applications.Business Editors/High Tech Writers BELFAST, N. Ireland & SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 10, 2001 Amphion JPEG JPEG in full Joint Photographic Experts Group Standard computer file format for storing graphic images in a compressed form for general use. JPEG images are compressed using a mathematical algorithm. IP cores for 130nm silicon offer 6-megapixel motion picture compression for CMOS image sensor A CMOS-based chip that records the intensities of light as variable charges similar to a CCD chip. Although initially used in less expensive digital cameras, the quality of CMOS sensors has improved steadily. CMOS sensors have advantages over CCDs. , movie-clip cameras, digital CCTV CCTV abbr. closed-circuit television CCTV closed-circuit television , video editing, PC webcam Amphion Semiconductor Ltd., the leading provider of semiconductor intellectual-property for multimedia, data security, wireless and broadband communications, today announces the immediate availability of its plug-and-play Motion JPEG accelerator IP cores - Codec, Encoder, and Decoder - for integration in 130nm ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. process technologies, and the latest generation of field programmable logic devices from Altera Corp. (APEX(TM) II family) and Xilinx, Inc. (Virtex(TM)-II series). Amphion CS6100 series Motion-JPEG encoder-decoder products are fully compliant with Baseline JPEG image compression standards as defined in ISO/IEC ISO/IEC International Organization for Standardization/International Electrotechnical Commission (ITU-T M 3000) 10918-1/2, and offer faster-than-real-time image processing that propels JPEG well beyond megapixel digital still camera applications. Silicon-proven JPEG cores for System-on-a-Chip "The migration of these cores to 130nm silicon gains the image processing designer a stunning 6-megapixel image compression at 30 frames per second," said J.G. Doherty, Amphion's CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. . "In fact, Amphion's JPEG compression quality is comparable to `I-frame only' MPEG-2 - that's MPEG-2 video without the motion compensation. That kind of real-time performance opens up a whole new range of possibilities for JPEG based systems, such as HDTV-sized color image processing at 60 frames per second." Amphion JPEG cores can be directly integrated into a variety of full motion and still image processing applications to enable an exciting array of digital video and multimedia applications: -- Hard-disk drive Digital Video Recording/Editing -- VGA-quality PC webcams; Video-conferencing -- Digital CCTV for remote/security surveillance -- Video-enabled Mobile Phone, Wireless PDA -- Networked Video/Image distribution, archiving -- Megapixel Digital Still Cameras "Amphion has pioneered application-specific cores for baseline JPEG image compression. We've won numerous JPEG sockets over the years and have seen Amphion JPEG proven successfully in silicon many times," Doherty added. 1000x better than RISC/DSP software solutions Amphion CS6100 series Motion JPEG cores process streaming frame-based images at rates up to 2.2 Gigabits per second (285 MegaSamples/sec x 8 bits per Sample) in devices using TSMC's 130nm (0.13-micron) standard cell process. The cores offer combined speed-power-area performance that is three orders of magnitude (1000x) better than RISC/DSP processor based software solutions and enables the compression-decompression of full color images at 60 frames per second with compressed image quality comparable to `I-frame' only MPEG-2. For consumer digital still camera applications, the Amphion CS6100 Encoder cores can compress full-color 4-megapixel images in 21 milliseconds at compression ratios up to 25:1 (i.e. 4 percent of the original picture file size) with imperceptible distortion to the viewer. Amphion CS6100 series Motion JPEG products are available now as off-the-shelf application-specific cores in targeted-netlist formats for 180nm, 150nm and 130nm ASIC processes, as well as the latest APEX(TM) II PLDs from Altera, and Virtex(TM)-II FPGAs from Xilinx:
Amphion CS6100 M-JPEG Encoder:
TSMC 130nm: 285 MegaSamples/sec, 285 MHz, 70K gates
Altera APEX II EP2A70-7: 59.40 MHz (Fmax), 8857 LE, 32256 ESB
Xilinx Virtex-II XC2V1000-5: 71.6 MHz (Fmax), 3413 SLICES, 5 BRAM,
9 MULTS
Amphion CS6150 M-JPEG Decoder:
TSMC 130nm: 185 MegaSamples/sec, 185 MHz, 60K gates
Altera APEX II EP2A15-7: 38.7MHz (Fmax), 8224 LE, 148736 ESB
Xilinx Virtex-II XC2V1000-5: 41.5 MHz (Fmax), 3422 SLICES, 4 BRAM,
9 MULTS
Amphion CS6190 M-JPEG Codec:
TSMC 130nm: 170 MegaSamples/sec, 170 MHz, 97K gates
Altera APEX II: key metrics available on request
Xilinx Virtex-II XC2V1000-5: 40.1 MHz (Fmax), 5800 SLICES, 5 BRAM,
9 MULTS
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"With the latest programmable logic devices, for example Xilinx Virtex-II series, we achieve encoding performance of 0.57 Gigabits per second. This enables standard-definition video processing at NTSC (National TV Standards Committee) The committee that developed the television standards for the U.S, which are also used in Canada, Japan, South Korea and several Central and South American countries. Both the committee and the standard are called "NTSC. or PAL rates in an FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. ," said Dr. Jill Hunter, Senior Designer at Amphion, and a member of the Joint Photographic Experts Group (image, body, file format, standard) Joint Photographic Experts Group - (JPEG) The original name of the committee that designed the standard image compression algorithm. JPEG is designed for compressing either full-colour or grey-scale digital images of "natural", real-world scenes. . "The encode and decode performance achievable makes these cores ideal for the most demanding frame-based image compression applications - without the need for host processor intervention." Amphion CS6100 Motion JPEG cores belong to an extensive range of standard products for video and imaging which also includes a Simple Profile MPEG-4 Video Decoder, a High-Definition MPEG-2 Video Decoder for ASIC, an MP@ML MP@ML Main Profile @ Main Level MPEG-2 Video Decoder for FPGA, and a Discrete Wavelet Transform In numerical analysis and functional analysis, a discrete wavelet transform (DWT) is any wavelet transform for which the wavelets are discretely sampled. The first DWT was invented by the Hungarian mathematician Alfréd Haar. core for JPEG2000 applications. Technical datasheets for Amphion products are available at http://www.amphion.com About Amphion Amphion is the leading supplier of application-specific cores for IP-based System-on-a-Chip (SoC) integrated circuit designs for multimedia, data security, wireless and broadband communications. Amphion delivers high-performance solutions for video and image compression, advanced encryption, and speech and channel coding with a comprehensive range of silicon-optimized products. Using proprietary techniques for the direct-mapping of processing functions and algorithms into hardware, Amphion develops and licenses semiconductor intellectual-property (SIP) cores that are close to optimal in terms of performance and power dissipation - typically 1000x better than competing solutions. Amphion cores operate either standalone, or interface directly to industry-standard RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. and DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive processors, and can be easily migrated through different generations of fabrication fabrication (fab´rikā´sh n the construction or making of a restoration. technology, thus preserving engineering investments in SoC design. Amphion is a privately-held company with corporate headquarters and engineering in Belfast, Northern Ireland, UK and worldwide sales and marketing headquarters in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. , USA. Amphion was formerly known as Integrated Silicon Systems Ltd, or ISS ISS See Institutional Shareholder Services (ISS). . For more information, visit http://www.amphion.com Notes to Editors: Amphion, The Amphion logo, and "Virtual Components for the Converging World" are trademarks of Amphion Semiconductor Ltd. All other brand names or product names are trademarks or registered trademarks of their respective owners. |
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