AmmoCore Receives Patent on Timing Exceptions; Unique Handling of Timing Exception Models Produces Accurate Top-Level Timing Results Early in Design Cycle.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--March 24, 2003 AmmoCore Technology, Inc., a provider of design implementation solutions for the rapid delivery of complex deep sub-micron system ICs, today announced it has received the issuance of US patent number 6,493,864 titled "Integrated Circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for Block Model Representation Hierarchical Handling of Timing Exceptions" from the United States Patent and Trademark Office The United States Patent and Trademark Office (PTO or USPTO) is an agency in the United States Department of Commerce that provides patent protection to inventors and businesses for their inventions, and trademark registration for product and intellectual property , related to accurate timing exception and correlation to top-level timing results. The technology is implemented in its Silicon Fabrix(TM) design platform and Fabrix(TM) software for IC physical design. "The grant of this patent further demonstrates the strength of our architecture," said Salah Werfelli, senior vice president of sales and marketing at AmmoCore. "When you select Fabrix(TM) as your physical design implementation solution, you are not simply buying a tool, you're getting a powerful, integrated design The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. platform that will not only help improve your design productivity today, but also let you scale to handle larger designs in the future without additional resources." SuperFlat(TM) Architecture The SuperFlat(TM) architecture allows the acceleration of the IC design process while optimizing critical IC design parameters such as density, timing and reliability. The SuperFlat(TM) architecture, which serves as the backbone for the Silicon Fabrix(TM) design platform, is based on SBlock(TM) modules, small subsets of the design, dynamically created through automatic partitioning To divide a resource or application into smaller pieces. See partition, application partitioning and PDQ. , and typically containing thousands of standard cells each. The SBlock(TM) modules are at a higher abstraction level See level of abstraction. than standard cells, and their relative size, on average, is smaller than functional blocks' size. By design, the SBlock(TM) modules correspond to the Register Transfer Level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) functionality. In a typical design, 90% of all nets, and the vast majority of critical paths are enclosed en·close also in·close tr.v. en·closed, en·clos·ing, en·clos·es 1. To surround on all sides; close in. 2. To fence in so as to prevent common use: enclosed the pasture. within the SBlock(TM) modules, where timing is easy to predict and close, and interconnect (1) To attach one device to another. (2) A physical port (plug, socket) or wireless port (transmitter, receiver) used to attach one device to another. lines are short enough to eliminate signal integrity issues. Timing Exception The timing exception patent focuses on two areas. The first area deals with the way Fabrix(TM) automatically configures and recognizes which terminals to extract into accurate SBlock(TM) module timing models. This capability lets designers partition A reserved part of disk or memory that is set aside for some purpose. On a PC, new hard disks must be partitioned before they can be formatted for the operating system, and the Fdisk utility is used for this task. the circuit at any boundary to create SBlock(TM) modules, without the limitations of user-specified exceptions. The second area deals with how Fabrix(TM) derives accurate top-level timing. It combines the data from the SBlock(TM) module timing models to derive top-level timing, then defines the SBlock(TM) module timing constraints based on the top-level timing. The result is early, accurate timing closure and predictability; so designers can be confident that timing closure can be achieved consistently, and with minimal design iterations. Availability The Fabrix(TM) software has been shipping since April 2002. It is available on Sun/Solaris platforms. About AmmoCore Technology, Inc. AmmoCore Technology provides design implementation solutions for the rapid delivery of extremely complex deep sub-micron system ICs. The Silicon Fabrix(TM) design platform, based on the patented SuperFlat(TM) architecture, enables chip designers to accelerate time-to-market, while reducing cost and improving chip performance. The company is headquartered at 2101 Tasman Drive, Suite 200A, Santa Clara, CA 95054. The company is privately held. For further information on AmmoCore, please visit our website at www.ammocore.com or call us at 408/748-4000. Note to editors: AmmoCore, the AmmoCore logo, SuperFlat, Fabrix, SBlock and Silicon Fabrix are registered trademarks or trademarks of AmmoCore Technology, Inc. All others are the property of their respective holders. |
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