Ambit Partners With Leading ASIC Vendors to Develop Static Timing Signoff; IBM, LSI Logic, Lucent, TI & VLSI Technology to sign off on BuildGates timing results.

SANTA CLARA, Calif.--(BUSINESS WIRE)--July 13, 1998--Ambit Design Systems, Inc. today announced plans to work with IBM Microelectronics (NYSE: IBM), LSI Logic (NYSE:LSI), Lucent Technologies Inc. (NYSE:LU), Texas Instruments Incorporated (NYSE:TXN) and VLSI Technology (NASDAQ:VLSI) to use Ambit's BuildGates* multimillion-gate synthesis tool for static timing signoff. These leading ASIC vendors have all agreed to work with Ambit to support processes modeled with the Open Library API (OLA) standard.

"In order to put more than 10 million gates onto a single chip, an accurate, and productive method to verify and sign-off on timing results is critical," said Venktesh Shukla, vice president of marketing for Ambit. "We expect the accuracy offered through OLA and the ability to get signoff quality timing information from a synthesis tool will significantly shrink our customers' verification cycles."

The static timing signoff process enables ASIC vendors to ensure that timing results meet customer specifications without requiring design teams to perform an exhaustive series of gate-level simulations. The process currently includes a full-chip static timing analysis tool, separate from the customers' synthesis engine, that creates excessive synthesis iterations as designers attempt to close timing for final sign-off.

In contrast, this agreement will allow BuildGates to provide an integrated signoff-quality, full-chip static timing engine with synthesis, allowing designers to perform chip-level timing, identify problem areas, and fix them efficiently within the synthesis tool. Designers receive a significant productivity boost, and ensure consistent timing throughout the synthesis flow.

OLA enables ASIC vendors to achieve greater precision on timing and power calculations while at the same time presenting a uniform interface to EDA vendor tools. OLA is based on proven compiler technology, which allows the use of tables and a flexible programming language to achieve these results.

About Ambit

Ambit Design Systems, Inc., the Superior Synthesis Alternative, is a privately held California company offering innovative synthesis solutions for high-end chip design. Ambit's logic synthesis tool, BuildGates delivers increased productivity on multimillion-gate chip designs without a significant change in the design methodology. Ambit technology is used by major microprocessor, multimedia and communications vendors worldwide, supported by leading ASIC manufacturers with advance process libraries, and endorsed by leading EDA companies. Upside Magazine recently placed Ambit among the "Hot 100" private companies for 1998. For more information, call 1-888-GO AMBIT or visit the Ambit website at www.ambit.com.

Quotes from partner companies: -0-

Jeff Hilbert, vice president of methodology, LSI Logic.

     "Every ASIC vendor has some qualification process that an IC
      design team has to pass through before they will guarantee
      that the silicon they manufacture will meet the timing that
      their customer expects. Traditionally, this has happened
      through an extensive series of gate-level simulations.
      However, as chip complexity grows, this becomes too time
      consuming. We're encouraged that a synthesis tool provider,
      like Ambit, had decided to make this industry-wide issue a
      priority."

Tom Willwerth, director of ASIC product development, Texas
Instruments.

     "Timing closure has quickly risen to the top of the list of most
      talked about issues facing the IC design community. The EDA
      industry has known for some time now that, in addition to
      providing best in class algorithms, new capabilities must
      emphasize expanding the information available to synthesis.
      Combining a chip-level timing verification capability with
      block level synthesis is a major step towards achieving the
      'Holy Grail' of timing correct-by-construction gate level
      netlists."

Bruce A. Beers, director of ASIC Products, IBM Microelectronics
Division.

     "Since we started working with Ambit, we've seen significant
      growth in customer demand for Ambit BuildGates libraries.
      Ambit's support for IEEE 1481 delay modeling and OLA is a
      strong assurance that our mutual customers will have
      accurate timing models for their designs."

Paul Wiscombe, director of design automation, VLSI Technology.

     "Ensuring a consistent timing view across the design flow is a
      key element in successfully implementing complex, high
      gate-count designs in 0.2-micron geometries and below.
      Integrating timing between synthesis and static timing
      analysis tools using the OLA standard aids timing
      convergence. Furthermore, it narrows the design productivity
      gap the industry faces when working with advanced deep
      submicron technologies."

Gary Gaspar, senior manager, ASIC design systems, Lucent Technologies.

     "As  system-on-chip complexity grows, timing closure and
      verification become increasingly large barriers to meeting
      early market demand for products. To continue to be a
      successful player in these markets requires continuous
      evolution of design capabilities consistent with the newer
      technology offerings. We expect that our work with Ambit on
      OLA libraries and static timing will eventually prove
      valuable toward meeting the challenging design goals of our
      customers."

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