Printer Friendly
The Free Library
19,595,263 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

Altos' Statistical Timing Library Models Proven on UMC's 65nm Process Using Extreme DA's GoldTime.


Variety[TM] LX Characterizes UMC's 65nm Standard Cell Library for Sensitivity to Process Variations

ANAHEIM, Calif. -- Altos Design Automation Inc. today announced that UMC UMC United Methodist Church
UMC United Microelectronics Corporation
UMC University Medical Center
UMC United Microelectronics Corp (Republic of China)
UMC University of Missouri-Columbia
 has qualified Altos' statistical timing model generator, Variety LX on UMC's 65nm standard cell library. This qualification effort means that designers can use Altos' Variety LX, UMC's 65nm process along with UMC's 65nm standard cell libraries to generate robust library views for statistical analysis and optimization. Statistical analysis and optimization play an important role in helping to overcome many of the challenges associated with designing at advanced process nodes in the presence of increasing process An increasing process is a stochastic process



where the random variables
 variability.

The qualification process involved the creation and validation of statistical timing models created by Variety LX accounting for process parameter variation. UMC then performed statistical timing analysis on critical signal paths using Extreme DA's GoldTime[TM] and all paths were found to have good correlation to the golden Monte Carlo Monte Carlo (môNtā` kärlō`), town (1982 pop. 13,150), principality of Monaco, on the Mediterranean Sea and the French Riviera.  SPICE simulation results. The mean path delay and mean plus/minus 3 sigma path delay were well within acceptable error tolerance levels.

"Statistical timing analysis can help reduce margins and improve design productivity when using 65-nanometer processes where chip performance is sensitive to parameter variations," said Darsun Tsien, UMC's vice president of design methodology. "A working statistical design flow needs library models that are derived from statistical-based process models along with silicon derived parameter variation measurements. We have confirmed that Variety LX can efficiently generate accurate models required by downstream statistical timing tools such as Extreme's DA GoldTime which enables improved yield prediction and optimization of circuit performance."

Jim McCanny, Altos CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  said, "By collaborating with UMC and Extreme DA in creating qualified statistical models, we have jointly created the foundation for our common customers to enjoy the benefits of using statistical design methods such as faster timing closure and lower power."

"Statistical timing analysis relies on detailed characterization of variations in the cell libraries used by designers," said Mustafa Celik, president and CEO of Extreme DA. "Our collaboration with Altos and UMC has produced a powerful, verified statistical flow that can improve IC performance and remove design pessimism pessimism, philosophical opinion or doctrine that evil predominates over good; the opposite of optimism. Systematic forms of pessimism may be found in philosophy and religion. . We are satisfying fabless semiconductor companies' demands for faster, more accurate timing closure and higher chip yields."

About Altos' Variety LX

Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Variety generates SSTA SSTA Saskatchewan School Trustees' Association
SSTA Scottish Secondary Teachers' Association (Scotland)
SSTA Sea Surface Temperature Anomaly
SSTA Statistical Static Timing Analysis
SSTA Security Seal Testing Authority
 models for a number of commercial SSTA products from a single characterization run.

About Extreme DA GoldTime

GoldTime[TM] provides timing analysis for performance sign-off of integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for  (IC) designs manufactured in advanced nanometer One billionth of a meter. Nanometers are used to measure the wavelengths of light. See angstrom and metric system.  (nm) processes. With its unique, patent-pending ThreadWave[TM] technology, GoldTime delivers 5X better speed and capacity over popular solutions in use today. GoldTime works with both nominal and statistical model libraries and supports corner-based and statistical design flows. See http://www.extreme-da.com for more information.

About UMC

UMC (NYSE NYSE

See: New York Stock Exchange
: UMC, TSE See Tokyo Stock Exchange.

TSE

1. See Tokyo Stock Exchange (TSE).

2. See Toronto Stock Exchange (TSE).
: 2303) is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC's SoC Solution Foundry strategy is based on the strength of the company's advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States United States, officially United States of America, republic (2005 est. pop. 295,734,000), 3,539,227 sq mi (9,166,598 sq km), North America. The United States is the world's third largest country in population and the fourth largest country in area. . UMC can be found on the web at http://www.umc.com.

About Altos

Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos' advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.

Privately held, Altos was founded in 2005 in Santa Clara Santa Clara, city, Cuba
Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba.
, CA. Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, CA 95117. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com

Variety LX is a trademark of Altos Design Automation, Inc. All other trademarks and registered trademarks are the property of their respective owners.
COPYRIGHT 2008 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2008 Gale, Cengage Learning. All rights reserved.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Jun 5, 2008
Words:720
Previous Article:Brekford International Announces Delivery of Advanced Anti-Terrorism Training Program to Unit of Department of Homeland Security.
Next Article:LabCorp(R) and Vanda Pharmaceuticals Collaborate to Offer Genetic Tests.
Topics:



Related Articles
UMC/VIRAGE TO ENABLE OPTIMAL IP AND CIRCUIT DESIGN FOR UMC.
ARM/TSMC SIGN IP PACT FOR 65- AND 45 NANOMETER TECHNOLOGIES.
Si2 Releases Power Extensions in ECSM 2.1 Standard for Design Libraries; Open Modeling Coalition Continues on Roadmap.
SYNOPSYS EXTENDS PRIMETIME/STAR-RCXT WITH STATISTICS.
Si2 Open Modeling Coalition Receives Contribution of Statistical Library Format.
Si2 Open Modeling Coalition Gains Access to Statistical Library Characterization Tool from Altos Design Automation.
Intrinsity Deploys Altos' Liberate(TM) to Create Libraries for Signal Integrity Analysis.
SIERRA UNVEILS INNOVATIONS FOR 45NM PHYSICAL DESIGN.
Altos' Cell Characterization Tools Used for TSMC's 40nm Libraries.
SYNOPSYS/UMC RELEASE 65-NANOMETER LOW POWER DESIGN FLOW.

Terms of use | Copyright © 2012 Farlex, Inc. | Feedback | For webmasters | Submit articles