Altera Unveils Technical Details of Its ARM- and MIPS-Based Excalibur Product Offerings.

Business Editors/High Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 25, 2000

Altera Corporation (Nasdaq:ALTR), a leading programmable logic device (PLD) supplier, today unveiled technical details of its RISC-based Excalibur(TM) embedded processor cores for system-on-a-programmable-chip (SOPC) designs (see related announcement today, "Altera Extends Excalibur Design Flow"). As part of its Excalibur product range, originally announced in June 2000, the XA and XM families provide unmodified embedded processor implementations of the ARM922T(TM) and the MIPS32 4Kc(TM) processors that run at 200 MHz, for Altera's APEX(TM) programmable logic architecture. The XA and XM Excalibur embedded processor solutions offer the single-chip integration, high performance, and reprogrammability needed for a broad range of applications in the communications, computing, networking, digital consumer, information storage, and industrial markets.

"Market access to industry-leading processor cores has been restricted to a limited number of companies because of the terms and conditions typically associated with core licensing models," said Rodney Smith, Altera chairman, president and CEO. "With Excalibur, Altera is able to provide a pre-licensed and complete SOPC solution that is readily accessible to all system designers. These new offerings can be used in a wide range of end applications, and offer a unique and powerful combination of time-to-market, flexibility, and integration when compared to ASICs, ASSPs, or stand-alone embedded processors."

The XA and XM Excalibur Solutions

The XA family is based on the ARM922T core, incorporating the Thumb(R) instruction set for both 16- and 32-bit systems. This core includes a memory management unit (MMU) and 8 Kbyte instruction and data caches, embedded into a fully-diffused area of the device known as the "stripe". In addition to the processor core and its caches, the stripe also contains up to 256 Kbytes of SRAM and 128 Kbytes of dual port RAM. Other embedded features include an SDRAM/DDRAM controller, UART, an external bus interface (EBI) to FLASH and SRAM, watchdog timer, timer counter, interrupt controller, embedded trace/debug logic, and up to six phase-locked loops (PLLs).

The MIPS-based XM devices use a MIPS32 4Kc core with 16Kbyte instruction, data caches, and a multiply/divide unit. The XM family makes use of the same stripe architecture and peripherals as the XA family.

With a focus on the benefits of standardization, Altera has chosen the AMBA(TM) bus-compliant Advanced High-performance Bus (AHB) from ARM as the interface between both the XA and XM embedded processor solutions and the array. The AMBA bus is an open standard, on-chip bus specification that was developed specifically for the interconnection and management of functional blocks that make up a system-on-chip (SOC). AHB is fast becoming the de-facto standard for SOC designs, and Altera is now extending this to the SOPC domain. The AHB serves the need for high-performance SOC as well as aligning with current synthesis design flows and being the choice of many third-party intellectual property (IP) providers. Advanced features of the AHB include support for multiple bus masters and pipelined burst transfers.

"The combination of ARM's industry-leading microprocessor core technology, the AMBA bus architecture, and Altera's programmable logic solutions will provide broad market access to all system level designers in need of meeting stringent time-to-market requirements," said Mike Muller, executive vice president for ARM Limited. "Altera's leading-edge system-on-a-programmable-chip solutions will allow designers complete system-level integration, while bringing advanced embedded processor technology to the broad marketplace."

"With the integration and design flexibility of Altera's APEX programmable logic architecture and our MIPS Technologies processor cores, Altera is able to provide customers with a truly complete system-on-a-programmable-chip solution with the Excalibur products," said John Bourgoin, MIPS Technologies, Inc. chairman, president and CEO.

Family Architecture

The XM and XA families are based on the proven process and technology of Altera's APEX 20KE PLD architecture and offer complete system integration on a single device. The APEX 20KE architecture uses a 0.18-micron, seven-layer-metal process. XA and XM devices implement the stripe in fully-diffused logic and use the APEX architecture to implement the PLD portion of the devices. The APEX feature set includes embedded system blocks (ESBs) for fast, efficient on-chip memory, and high-bandwidth I/O capabilities, providing an ideal silicon delivery vehicle for SOPC designs.

Pricing and Availability

Quartus software support for the new devices will be available to beta customers in October 2000. A production release of the Quartus tool providing full software support for Excalibur products will be available in January 2001 and will be a part of the Altera development tools subscription package. Initial samples of the XA10 device, the first member of the XA family, will be available in December, while XM10 samples will be available in Q1 2001. The remaining family members will be available during the first half of 2001. Volume production prices will start at $35 for the XA1 and XM1 devices.

Safe Harbor Notice

This press release contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "will," "expects," or "anticipates." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that the Company's products may not be available according to the current schedule. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.

About Altera

Altera Corporation, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Altera, The Programmable Solutions Company, Excalibur, APEX, Quartus, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.

ARM and Thumb are registered trademarks and ARM922Tand AMBA are trademarks of ARM Limited. All other trademarks are the property of their respective holders.

MIPS is a registered trademark and MIPS-based, MIPS32 and 4K are trademarks of MIPS Technologies, Inc.