Altera Targets High-End ASIC Designs With FLEX 10K Architecture; Industry's First Embedded Programmable Architecture Provides 100,000 Gate Capacity; Implements Memory Functions As Efficiently As Embedded Gate Arrays.SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--March 20, 1995--Altera Corporation (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :ALTR) today unveiled the architecture for its FLEX 10K family of programmable logic devices. The first family to feature an embedded array architecture, FLEX 10K moves programmable logic See PLD. further into the mainstream of gate arrays and other ASICs. Its breakthrough architecture allows it to implement memory functions as efficiently as embedded gate arrays, the fastest growing type of gate array. By embedding the needed functions into the silicon using all mask layers, embedded gate arrays provide reduced die area and increased speed compared to standard gate arrays. "At gate densities over 50,000 gates, embedded gate arrays are becoming more popular and economical because of the need to efficiently implement complex functions," said Bryan Lewis Bryan Lewis (b. Alliston, Ontario) is a Canadian municipal politician and a former referee and Director of Officiating for the National Hockey League. His first NHL experience was in the 1966-67 NHL season. , Dataquest's director and principal analyst for the ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. service. "For a programmable logic device to be effective at these high gate counts, it needs the ability to implement memory functions as efficiently as embedded gate arrays," Lewis concluded. "The innovations in the FLEX 10K architecture enable programmable logic, for the first time, to implement designs now being done exclusively in gate arrays," said Erik Cleage, Altera's vice president of marketing. "We can now execute memory and specialized logic functions with the same kind of efficiency and speed as embedded gate arrays." This breakthrough allows the FLEX 10K family of devices to address designs as large as 100,000 gates. Designs over 10,000 gates invariably in·var·i·a·ble adj. Not changing or subject to change; constant. in·var i·a·bil need to use large functions,
most predominantly memory, but also arithmetic functions,
microcontrollers, and microperipherals, that do not fit well into
existing programmable architectures. According to according toprep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. Dataquest, over 40 percent of the gate array design starts use some form of memory function. To date, programmable logic could be used to implement small memory functions, but only with speed and efficiency penalties. In order for programmable logic to directly address the needs of the ASIC designer, the programmable solution must address these popular functions without speed, utilization or cost penalties. Embedded Functionality Provides the Key The FLEX 10K architecture provides the solution to this dilemma. Its unique structure allows the implementation of random logic, but also provides embedded array blocks (EABs), which can implement a variety of memory and specialized logic functions as efficiently as embedded gate arrays. The FLEX 10K architecture provides two ways of implementing functions, either in Logic Array Blocks (LABs) or Embedded Array Blocks (EABs). Logic Array Blocks are groups of eight enhanced Logic Elements (LEs). These LEs are 100 percent interconnected with other LEs in the same LAB. Altera has greatly increased the number of LABs in FLEX 10K devices, with the largest device containing over 4 times as many LABs as the largest FLEX 8000 device, the EPF EPF early pregnancy factor. 81500A. Embedded Array Blocks - Embedded Array Blocks (EABs) can be represented as a "Sea of Programmable Bits" which can be configured to perform a number of memory and logic functions. Each EAB EAB Emerald Ash Borer (insect) EAB Environmental Appeals Board (EPA) EAB Educational Activities Board (IEEE) EAB Environmental Advisory Board EAB Egyptian American Bank can support up to 2K bits of RAM or ROM, and can be configured in 2048x1, 1024x2, 512x4 or 256x8. EABs can also be configured to support FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods. FIFO - first-in first-out and Dual-Port RAM as well. Additionally, EABs can be cascaded together to make wider or deeper memory configurations. EABs are also used to create optimized logic functions, such as multipliers, ALUs, and DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive functions. Enhanced FastTrack Interconnect LABs and EABs are connected together by an enhanced FastTrack Interconnect scheme. The FastTrack Interconnect connects EABs and LABs by rows and columns of wire that span the length of the die. In an enhancement to the FastTrack, Altera added row lines providing 50% more routing resources, necessary for devices of this capacity. FLEX 10K maintains the predictable interconnect delays characteristic of all Altera architectures, a decided advantage over FPGAs. MAX+PLUS II Design Support FLEX 10K devices will be supported by Altera's MAX+PLUS II development system for PC and workstation platforms. Enhancements will be made to MAX+PLUS II to support the special features of the FLEX 10K architecture. These enhancements include the addition of a RAM/ROM compiler, a library of embedded functions to exploit the unique features of the EABs, and simulator enhancements to allow the viewing of values within the Embedded Array Blocks. MAX+PLUS II offers an architecture independent development environment, which enables the designer to target designs to any of Altera's FLEX 10K, FLEX 8000, MAX 9000, MAX 7000, MAX 5000, or Classic families of general-purpose programmable logic. MAX+PLUS II provides seamless integration An addition of a new application, routine or device that works smoothly with the existing system. It implies that the new feature or program can be installed and used without problems. Contrast with "transparent," which implies that there is no discernible change after installation. with tools from Cadence, Data I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output , Mentor Graphics, Synopsys, Viewlogic and other leading EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. vendors. Availability The FLEX 10K family contains seven members ranging in density from 10,000 to 100,000 usable gates, up to four times the density of today's FPGAs. Outlined below are the members of the family: -0-
Device Typical Gates Usable Gate RAM Capacity Availability
Range (Bits)
EPF10K100 100,000 69,500-170,000 26,624 4Q95 EPF10K70 70,000 48,000-117,000 18,432 1996 EPF10K50 50,000 38,500-115,000 20,480 3Q95 EPF10K40 40,000 31,000- 92,000 16,384 1996 EPF10K30 30,000 23,000- 69,000 12,288 1996 EPF10K20 20,000 16,000- 62,000 12,288 1996 EPF10K10 10,000 8,000- 31,000 6,144 1996 -0- About Altera Altera Corporation, founded in 1983, is a world-wide leader in high-performance, high-density programmable logic devices and associated computer aided engineering (application) Computer Aided Engineering - (CAE) Use of computers to help with all phases of engineering design work. Like computer aided design, but also involving the conceptual and analytical design steps. (CAE (1) (Computer-Aided Engineering) Software that analyzes designs which have been created in the computer or that have been created elsewhere and entered into the computer. ) logic development tools. Programmable logic devices are semiconductor chips that offer on-site programmability to customers. The chips are programmed using tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. The company offers the broadest line of CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. programmable logic devices that address high-speed, high-density, and low-power applications. Altera products serve a broad range of market areas, including telecommunications, data communications, computers, and industrial applications. Altera common stock is traded on the Nasdaq National Market using the symbol ALTR. -0- Note to Editors: Altera, MAX, MAX+PLUS and FLEX are registered trademarks, and FLEX 10K, FLEX 8000, MAX 9000, MAX 7000, MAX 5000, MAX+PLUS II, FastTrack and specific device designations are trademarks of Altera Corporation. All other trademarks are the property of their respective holders. CONTACT: Altera Corporation Robert K. Beachler or Cliff Tong, 408/894-7000 |
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