Altera Ships World's Largest Programmable Logic Device.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--June 30, 2000

Altera Corporation (Nasdaq:ALTR) today announced shipment of the programmable logic industry's largest device, establishing integration density leadership for system designers, and a 35 percent density advantage over the nearest industry competitor. The new 1.5-million gate (2.5-million system gates) APEX(TM) EP20K1500E allows implementation of complete system-on-a-programmable-chip (SOPC) solutions, and expands Altera's offering of high-density 1.8-volt CMOS programmable logic devices (PLDs) built using a 0.18-micron, eight-layer-metal process. The EP20K1500E device is ideal for leading-edge communications applications such as Layer 3 Routers and Switches, Wideband CDMA, Baseband Signal Processing, ATM Cell Processing, Traffic Management, Terabit Routers, Switch Fabrics, and Enterprise Storage Network Equipment.

Altera's APEX EP20K1500E device contains 51,840 logic elements (LEs), the basic building block of programmable logic commonly used to judge device density. Together, Altera's new EP20K1500E and the 1-million gate (1.8-million system gates) EP20K1000E devices make the industry's two largest PLDs available for development today.

Altera's APEX 20K1500E device continues to offer capabilities not seen in the programmable logic industry, including the True-LVDS(TM) solution which enhances the 16-channel low-voltage differential signaling (LVDS) I/O performance to 840 Mbps (see related announcement: Altera Announces True-LVDS(TM) Solution; Increases Data Transfer Rates to Industry-Leading 840 Mbps, June 10, 2000). Additional I/Os such as SSTL 3/2, GTL+, AGP, LVTTL, LVCMOS, HSTL, PCI 66/PCI-X, and T1/E1 interfaces are also supported. No other programmable logic vendor offers this combination of high-density integration and advanced features.

"With shipments of the APEX EP20K1500E and EP20K1000E devices, Altera has regained worldwide high-density leadership in the programmable logic arena," said Erik Cleage, Altera senior vice president of marketing. "In the past, designers had to sacrifice performance by partitioning designs across multiple PLDs. By supplying the industry's largest devices, customers can develop complete systems by integrating multiple high-speed intellectual property cores all on a single programmable logic device."

Effective Implementation in Communication Systems

Altera's EP20K1500E device offers design flexibility and efficiency for high-performance, system-on-a-programmable-chip applications. The abundance of LEs and embedded RAM make the EP20K1500E device an ideal solution for incorporating many intellectual property (IP) cores needed for advanced communication systems. For example, a typical modulator used in wireless base-stations requires a Reed Solomon Encoder/Decoder, Viterbi Decoder, Interleaver/Deinterleaver, FIR Filter, and a Numerically Controlled Oscillator (NCO). These cores together consume about 5,250 LEs, which is equivalent to 10 percent of an EP20K1500E device. Altera's new Nios(TM) embedded processor core consumes approximately 1,000 logic cells, equivalent to just two percent of an EP20K1500E device, leaving most of the device resources available for customized peripherals and logic functions, as well as multiprocessor system implementation. By offering IP as easy-to-use parameterized cores, designers can reduce overall design time and focus their efforts on value-added parts of the system.

The APEX(TM) 20KE Family

Altera's APEX 20KE family consists of 10 devices spanning from 30,000 to 1.5 million gate densities (113,000 to 2.5 million maximum system gates). Altera's unique MultiCore(TM) architecture combines look-up table (LUT)-based logic, flexible embedded memory, and high speed PLLs. A total of 4 PLLs can be used in the APEX 20KE family. With clock multiply/divide, phase shift, and clock skew, these features allow complete solutions for communications applications. The MultiCore architecture consists of large blocks called MegaLAB(TM) structures, which are optimized for core-based designs, and are connected via Altera's continuous FastTrack(R) interconnect routing structure. An embedded system block (ESB) within a MegaLAB structure contains 2,048 programmable bits that can be configured to support on-chip memory, including dual-port RAM and ternary content-addressable memory (CAM).

Design Tools

The EP20K1500E is supported by version 2000.05 of the Quartus(TM) development software, Altera's fourth-generation development environment. Altera's Quartus software meets the challenges of designing for multi-million gate devices and enables SOPC design methodology. It also features the SignalTap(TM) embedded logic analysis tool for in-system hardware debugging Quartus software supports system-level designs and features links as good as native to industry leading, third-party tools from Mentor Graphics, Synopsys, Synplicity, Viewlogic, and other leading EDA vendors.

The Quartus development software supports major operating systems, including Windows NT, Windows 98, Sun Solaris, and HP-UX. Annual subscription for the Altera development tools is $2,000 for a node-locked PC license, which includes full-featured Quartus and MAX+PLUS(R) II development software and 12 months of software upgrades. New or existing customers may obtain a software subscription at the Programmable eStore on the Altera web site, http://www.altera.com or from Altera distributors worldwide.

Availability, Packaging, and Pricing

The Altera EP20K1500E programmable logic device is available now. Prototype pricing for the EP20K1500E starts at $4,995. For high-volume production quantities, mask programmed logic device (MPLD) versions are priced at approximately $100. Packaging options will include Altera's 652-pin BGA and 1020-pin FineLine BGA(TM) packages.

About Altera

Altera Corporation, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com. A photograph can be found at http://www.businesswire.com/altera.

Note to Editors: Altera, The Programmable Solutions Company, APEX, True-LVDS, Nios, MultiCore, MegaLAB, FastTrack, Quartus, SignalTap, MAX+PLUS, FineLine BGA, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.