Altera Ships APEX 20K, Programmable Logic Industry's First System-on-a-Programmable-Chip Solution.

SAN JOSE, Calif.--(BUSINESS WIRE)--April 16, 1999--

Altera Corporation (Nasdaq:ALTR) today revealed that it has shipped, in the first quarter of 1999, its highly anticipated programmable logic device architecture, the revolutionary APEX(TM) 20K. The PLD industry's first architecture to successfully integrate product-term and look-up-table functionality along with embedded memory, the APEX 20K family will offer breakthrough integration of entire complex systems on a single programmable chip. Additionally, initial product family, the APEX 20K, provides device density of up to 1 million gates, with enhanced in-system performance that supports 64-bit/66 MHz PCI compliance. The first APEX 20K device, the 400,000-gate EP20K400, is now shipping and is supported by Altera's advanced Quartus(TM) design environment and backed by a full complement of intellectual property (IP) cores -- including processors and peripherals, telecom and database functions, DSP functions, and PCI and other bus interfaces -- from Altera and its Altera Megafunction Partner Program (AMPPSM) member companies.

"The combined offering of APEX 20K, Quartus, and IP marks a new era of capability for system designers who have used either PLDs or ASICs. This is a complete solution that gives our customers unsurpassed design efficiency and total control of the system design," said Erik Cleage, Altera senior vice president of marketing. "By implementing an entire system on a single APEX chip, developers can increase performance and still have the flexibility to change the design at any time. Similarly, parameterization tools and automated synthesis technology built into the Quartus design environment provide designers with the confidence they need to quickly and easily implement and customize IP cores. This combination allows Altera to continue delivering on the promise of high density, high performance PLDs for fast time-to-market."

APEX 20K's efficient architecture enables unprecedented integration, allowing significant improvements in system cost and performance -- key requirements for system designers. For example, a single EP20K400 device can integrate all of the components required to build a 1-Gigabit Ethernet 8-port switch, including a MIPS-compatible processor core, MAC interfaces, FIFOs, PLLs, memory, CAM, cache memory, and all associated interfaces.

"APEX 20K devices provide us with a programmable system integration solution at a performance level that is unmatched by any other PLD supplier," said Joe Berger, vice president of engineering at Silicon Light Machines, a leading developer of high-resolution projection display technology. "The flexibility of the APEX 20K MultiCore(TM) architecture, which integrates the functionality of look-up table logic, product-term logic and memory, enables us to meet our high bandwidth HDTV requirements on a single device."

EP20K400 Features

The first member of the APEX family, the EP20K400, began shipping in volume today. The EP20K400 device is fabricated on a 0.25-micron (drawn), six-layer metal SRAM process and features 16,640 logic elements, 104 embedded system blocks, 1664 macrocells, and 212,992 bits of on-chip RAM for a combined total of approximately 400,000 gates. The on-chip RAM can be configured as dual-port RAM, ROM, or as product-term logic. The EP20K400 device features 125 MHz system performance and enhanced phase-locked loop (PLL) with 1x, 2x and 4x clock rate multiplying options. Other members of the family are expected to range in density from 100,000 gates to as many as 1 million gates.

New Design Tools

The new APEX family will be fully supported by Altera's fourth-generation development environment, Quartus. Quartus was developed to support system-level designs with powerful features such as nSTEP(TM) incremental compilation, CoreSyn(TM) synthesis optimization, the SignalTap(TM) logic analysis solution, and integrated support for workgroup computing and industry-standard revision control software. Quartus also features good-as-native links to industry-leading third-party tools from Cadence, Exemplar Logic, Mentor Graphics, Model Technology, Synopsys, Synplicity, Viewlogic, and other leading EDA vendors.

"Altera's new APEX 20K family coupled with Quartus software greatly improves our design and verification methods," said Richard Miller, CEO, VMLabs Inc. "The SignalTap logic analysis solution allows us to verify device functionality on large system-sized designs in real time and to capture and analyze any internal signal in Altera's APEX 20K PLD family, thus reducing the need for time-consuming board level debug."

Altera's Quartus development environment will be distributed at no extra cost to current subscribers of Altera's development tools program. Annual subscription rates for the program are $2,000, which includes Altera's Quartus and MAX+PLUS(R) II development environment and 12 months of upgrades and technical support. Quartus provides support for Windows NT, Windows 98, Windows 95 operating systems on the PC, as well as Sun Solaris and HP-UX systems. Support for the Intel-based computing environments bears out the continuing penetration of the PC platform into high-end digital design development spaces.

Efficient IP Integration

By implementing IP as easy-to-use parameterized cores, designers can reduce overall design time, and focus more of their efforts on value-added parts of the system. Altera offers this IP in the form of Altera-developed Megacores(TM) and optimized cores from third-party Altera Megafunction Partner Program members. Altera Megacores and AMPP megafunctions include PCI and other bus interfaces, processors and peripherals, DSP cores, and communications functions. Altera's Quartus(TM) design environment simplifies IP integration through its OpenCore(TM) test-drive feature, MegaWizard(TM) plug-in manager, and CoreSyn(TM) synthesis algorithm. CoreSyn is a revolutionary tool that targets elements of the design to the performance-optimizing PLD construct (look-up table, product term, or memory block) within the APEX 20K architecture.

Availability, Packaging, and Pricing

The EP20K400 is shipping now in the 655-pin PGA package. Other package options include a 652-pin BGA and 676-pin Fineline(TM) BGA packages. Volume pricing by year-end 1999 will be $200 in the 676-pin FineLine BGA package.

Safe Harbor Notice

This press release contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "expects," "believes," "anticipates," "projects," or "intends." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risks that the Company's products will not satisfy customer demands, that other companies will develop products with higher densities than those offered by the Company, and that yields will not be sufficient to support projected pricing. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.

About Altera

Altera Corporation, The Programmable Solutions Company(TM), was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.

Note to Editors: Altera, The Programmable Solutions Company, APEX, System-on-a-Programmable Chip, Quartus, AMPP, MultiCore, nSTEP, CoreSyn, MAX+PLUS, SignalTap, OpenCore, MegaWizard, MegaCore, and FineLine BGA and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.