Altera Introduces The Nios Embedded Processor, Industry's First RISC-Based Embedded Processor Developed for SOPC Integration.

Business Editors/High Tech Writers

Embedded Processor Forum

SAN JOSE, Calif.--(BUSINESS WIRE)--June 12, 2000

Altera Corporation (Nasdaq:ALTR) today introduced the Nios(TM) embedded processor, the industry's first general-purpose RISC-based embedded processor core optimized specifically for programmable logic, and the Excalibur(TM) development kit featuring the Nios embedded processor core. The Nios core represents the first phase of Altera's Excalibur embedded processor solutions also announced today (see related release titled "Altera Unveils Strategy for Embedded Processor Integration in System-on-a-Programmable-Chip Design"), geared toward providing a comprehensive solution for system-on-a-programmable-chip (SOPC) designs. The Nios embedded processor can achieve 50 MIPS performance at a volume price point of $5 and provides a 16-bit instruction set, 16- or 32-bit datapaths, and a five-stage pipeline that executes an average of one instruction per clock cycle.

"The Nios soft core embedded processor is configurable and scalable, providing a flexible and highly robust SOPC solution for system integration," stated Cliff Tong, vice president of corporate marketing at Altera. "By combining the Nios processor with our APEX(TM) devices and the comprehensive software and hardware tools contained in the Excalibur Development Kit, designers now have all the elements necessary to quickly and efficiently develop SOPC designs for their specific applications."

The cost-effective Nios embedded processor was created from the ground up to leverage Altera's programmable logic architectures. The Nios embedded processor targets those applications in the communications, computing, and industrial markets that currently are served by stand-alone embedded processors and microcontrollers, or those that are embedded within application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs).

The flexibility and scalability of the Nios soft core embedded processor will allow it to be used in a wide range of designs. A Nios 16-bit embedded processor core running a program stored in the on-chip memory within an Altera PLD, makes an effective sequencer/controller that can take the place of a hard-coded state machine. A Nios 32-bit embedded processor core with external FLASH program storage and large external main memory offers comparable processing power and much greater flexibility relative to many stand-alone embedded processors. The scalable nature of the Nios embedded processor allows it to be instantiated multiple times in a single Altera PLD and configured to act as a specialized network processor.

Nios(TM) Embedded Processor Development Environment

Using Altera's MegaWizard(TM) interface, the designer can map a system and configure memory and peripherals. For example, the designer can choose from a variety of widths and speeds of memory as well as peripheral types. Furthermore, the Nios embedded processor core can be extended in three ways:

      --  Adding conventional memory-mapped peripherals on-chip
      --  Mapping readable/writeable devices into the processor's
        register file
      --  Adding user-designed function blocks directly into the
        processor's ALU

The instruction set within the Nios embedded processor core is targeted for compiled embedded applications, and includes instructions especially useful in embedded systems (e.g., single-instruction bit-test-and-skip). The core is supported by a debugger that provides hardware breakpoints and run-control over the existing JTAG pins. The debugger communicates with the processor hardware over Altera's standard MasterBlaster(TM) or ByteBlaster(TM) cables.

The Nios embedded processor is fully supported by Red Hat's GNUPro embedded system development tools created by Cygnus, a division of Red Hat. The GNUPro tool suite provides a robust and open development platform for embedded system design that includes a C/C++ compiler, assembler and debugger. Future plans include support for the Red Hat eCoS real-time operating system.

Initially, the Nios embedded processor core will be released with peripheral blocks that include a universal asynchronous receiver transmitter (UART), parallel In/Out (PIO), counter/timers, and SRAM and Flash external memory interfaces. Additional peripherals will be provided in the future.

The APEX(TM) Architecture -- Altera's Flagship SOPC Integration

Platform

The APEX device family ranges from 60,000 to more than 1.5 million gates (160,000 to over 2.5 million maximum system gates) and is shipping on a 0.18-um, six-layer-metal process.

The APEX architecture meets the system-level design challenge by not only offering industry-leading device density, but also by incorporating advanced features including embedded content addressable memory (CAM) and the True-LVDS solution capable of 840 Mbit/sec I/O data rates. The Nios embedded processor core consumes approximately 1,000 logic cells, equivalent to 12 percent of an APEX EP20K200E device or just two percent of an APEX EP20K1500E device, leaving most of the device resources available for customized peripherals and logic functions.

Pricing and Availability

The Excalibur Development Kit featuring the Nios embedded processor core is available for order now and is priced at $995. The development kit includes the Nios embedded processor core, a version of Altera's Quartus(TM) design tools, the Red Hat GNUPro suite of embedded system design tools, a system development board populated by an APEX EP20K200E device, and an Altera ByteBlaster download cable.

Hands-on workshops will be held throughout the United States in June, July, and August. Workshops will be conducted in Europe and Japan in September and October. These free workshops will provide hardware and software engineers an opportunity to evaluate the Nios embedded processor and experience the creation of a working system design using the Excalibur Development Kit.

About Altera

Altera Corporation, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Note to Editors: Altera, The Programmable Solutions Company, Nios, Excalibur, APEX, MegaWizard, MasterBlaster, ByteBlaster, Quartus, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.