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Altera Enhances Performance Leadership Through Array Driver Technology.


Business Editors/High Tech Writers

SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.--(BUSINESS WIRE)--Feb. 19, 2001

Altera Corporation (Nasdaq:ALTR), a leading supplier of programmable logic devices (PLDs), today announced the implementation of advanced array driver technology and flip-chip packaging available in its new Mercury(TM) device family. For the first time in the PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user.  industry, these two leading-edge technologies have been incorporated in a programmable device. The state of the art array driver technology implements I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 pads within the center of the device core. This dramatically reduces the distance traveled by the signals from logic to I/O pads to solder balls, improving the overall I/O performance and supporting the high speeds needed for Clock Data Recovery (CDR (1) See CD-R and extension.

(2) (Call Detail Reporting) See call accounting.

(3) (Common Data Rate) A standard sampling rate for digital video for 480i and 576i systems. The rate is 13.5 MHz. See ITU-R BT.
). Additionally, the high I/O performance requirements of the Mercury device family required coordinated development of silicon design process and the packaging. By incorporating printed circuit board (PCB PCB: see polychlorinated biphenyl.
PCB
 in full polychlorinated biphenyl

Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound.
) requirements into package considerations, the Mercury silicon was able to place multiple phase-locked loops Phase-locked loops

Electronic circuits for locking an oscillator in phase with an arbitrary input signal. A phase-locked loop (PLL) is used in two fundamentally different ways: (1) as a demodulator, where it is employed to follow (and demodulate) frequency or
 (PLLs), I/O bands, and high speed serial receive and transmit channels in a manner best suited for PCB layout.

"The layout process for the Mercury device package uses state of the art substrate and assembly technology to combine optimal placement of package balls from a PCB perspective with optimal silicon placement of the flip-chip bumps," said Tarun Verma, Altera director of package development. "The methodology derived here will allow us to continue offering the most effective packaging solutions for high performance PLDs."

The Mercury family extends Altera's device packaging leadership as a means of obtaining I/O performance levels of up to 1.25 Gbps and in order to support advanced high-speed communications applications. This enables the implementation of up to 18 channels all toggling simultaneously at 1.25 Gbps, for a total device bandwidth of 45 Gbps. The array driver implementation also eliminates the limitation on I/O count created by the length of the device perimeter, and therefore enables higher I/O counts for a given die size.

"Altera has worked closely with the Kyocera package design team to design and optimize our substrate layout to meet Altera's device performance objectives." said Fritz Johnson, National Sales Manager sales manager ngerente m/f de ventas

sales manager ndirecteur commercial

sales manager sale n
 for Organic Products, Kyocera America, Inc. - the world's leading manufacturer of advanced flip chip A chip packaging technique in which the active area of the chip is "flipped over" facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done  substrates. "Kyocera's ability to route the signal I/O pads from the device core enables Altera's array driver technology to achieve improved I/O performance."

Advanced Flip-Chip Technology

Altera has shipped over 75,000 devices utilizing flip-chip packaging technology since the introduction of flip-chip to the PLD industry in the APEX(TM) EP20K400 in September 1999. These packages provide a thermally optimized solution by distributing pins across the face of the die and improving heat dissipation Noun 1. heat dissipation - dissipation of heat
chilling, cooling, temperature reduction - the process of becoming cooler; a falling temperature
. Flip-chip technology also enables greater flexibility in pin placement for enhanced migration capabilities, faster time-to-market for PLD products, improved I/O performance, and a simplified package assembly process.

The World's First Programmable ASSP (Application Specific Standard Part) An ASIC chip that is designed as a generic device for a particular market. Whereas an ASIC is typically used only by its creator, ASSPs are used by many different companies in the design of their products. See ASIC.  

Mercury, the world's first programmable ASSP, provides up to 18 channels of CDR transceivers and performance optimized programmable logic in a single device in order to address key communications requirements. CDR transceivers eliminate the frequency barriers faced by source synchronous systems by offering data rates of up to 1.25 Gbps and support for commonly used I/O standards such as Gigabit Ethernet, SONET, IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields.  1394, and Fibre Channel. This is combined with a programmable core built for bandwidth, using a prioritized interconnect structure, distributed multiplier circuitry, dedicated interfaces to high speed external memory, and quad-port embedded RAM blocks. Mercury devices are ideally suited for serial backplane, chip-to-chip, and line side communications applications.

About Altera

Altera Corporation, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC SOPC System on a Programmable Chip
SOPC Special Operations Preparation Course
SOPC Second-Order Power Control
SOPC Shuttle Operations and Planning Center
SOPC 1-Stearoyl-2-Oleoyl-Sn-Glycero-3-Phosphatidylcholine
SOPC Shaastra Online Programming Contest
) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market Nasdaq stock market

The first electronic stock market listing over 5000 companies. The Nasdaq stock market comprises two separate markets, namely the Nasdaq National Market, which trades large, active securities and the Nasdaq Smallcap Market that trades emerging growth companies.
 under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Altera, The Programmable Solutions Company, Mercury, APEX, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.
COPYRIGHT 2001 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2001, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:Feb 19, 2001
Words:739
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