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Altera Broadens Density Range for APEX Device Family, Including Industry's Largest PLD.


SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 27, 1999--

Altera Corporation (Nasdaq:ALTR) today announced that it will broaden its line of APEX(TM) programmable logic devices by adding two members; the EP20K1500E, the PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user.  industry's highest density device; and the EP20K60E, the lowest-cost APEX device. The new members effectively widen the family's density range from 60,000 gates (160,000 maximum system gates) up to 1.5 million gates (2.5 million maximum system gates). According to a recent Dataquest report, less than 10 percent of gate array designers engage in designs containing more than 2 million gates; thus, Altera's APEX device family addresses the density needs of more than 90 percent of today's designs. APEX device applications include telecommunication switches, cellular base stations, routers, and ATM concentrators.

"The new APEX devices will enhance the product options at both ends of the family spectrum," said Craig Leclair, Altera director of components marketing. "In addition to its many performance enhancing features, the EP20K60E will be the low-cost leader in its density class. At the same time, the EP20K1500E, which offers more than twice the logic cells and memory currently available in a single PLD, allows for very-large-scale system integration, including enough logic and memory resources to easily incorporate a MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second.  R3000-Class processor core and multiple DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive  functions to develop an entire digital system."

The APEX device family features the innovative MultiCore(TM) architecture which includes look-up tables, product-terms and memory to satisfy the system-level requirements of a wide variety of designs. The EP20K60E will include 2,560 logic elements (LEs) and 32,768 bits of RAM, while the EP20K1500E will feature an industry-high 54,720 LEs and 466,944 bits of RAM, making it the largest available PLD, ideal for implementing System-on-a-Programmable-Chip(TM) solutions.

The EP20K1500E will be developed using an industry-leading 0.15-micron, 1.8-V process. The EP20K60E will be developed on an advanced 0.18-micron, 1.8-V process. Features associated with both APEX devices include 64-bit, 66 MHz PCI (1) (Payment Card Industry) See PCI DSS.

(2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus).
 compliance, multiple PLLs, advanced I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 standards including SSTL SSTL Surrey Satellite Technology Ltd
SSTL Stub Series Terminated Logic
SSTL Site Specific Target Level
SSTL Solid State Track Link
 -3/-2, GTL GTL - Gunning Transceiver Logic +, HSTL HSTL High-Speed Transceiver Logic (family of logic integrated circuits)
HSTL High-Speed Transistor Logic (electronics) 
, AGP (Accelerated Graphics Port) A high-speed 32-bit port from Intel for attaching a display adapter to a PC. It provides a direct connection between the card and memory, and only one AGP slot is on the motherboard. , and CTT CTT Correios (Portuguese Postal Service)
CTT Certified Technical Trainer
CTT Charity Technology Trust
CTT Cholesterol Treatment Trialists' (collaboration)
CTT Common Task Training
, and content-addressable memory (CAM), the first-ever for programmable logic. CAM, a memory technology developed from RAM, accelerates applications requiring fast searches of databases, lists, and patterns. CAM simultaneously compares input data against an entire list of pre-stored entries in a single clock cycle, thereby enabling a significant reduction in search time.

The EP20K1500E features support for 4 PLLs and low-voltage differential signaling Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over cheap, twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks  (LVDS (Low Voltage Differential Signaling) A transmission method for sending digital information. LVDS sends data over data high and data low lines rather than data and ground. ) with data rates of 622 Mbits/s. Altera's APEX family is the only PLD family with support for LVDS. This new data interface standard provides significant advantages for many different applications, such as imaging systems, LAN (Local Area Network) A communications network that serves users within a confined geographical area. The "clients" are the user's workstations typically running Windows, although Mac and Linux clients are also used.  stackable hubs, and telecommunication switches. When high-bandwidth communication is required, LVDS provides a robust high-speed and low-power interface solution.

New Design Tools

The EP20K60E and EP20K1500E will be fully supported by Altera's fourth-generation development environment, Quartus(TM). The Quartus software was developed to support system-level designs and features good-as-native links to industry-leading third-party tools from Exemplar Logic, Model Technology, Synopsys, Synplicity, Viewlogic, and other leading EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  vendors.

Altera's Quartus development environment is distributed at no extra cost to current subscribers of Altera's development tools program. Annual subscription rates for the program are $2,000 for a node-locked PC license, which includes Altera's Quartus and MAX+PLUS(R) II development environment and 12 months of upgrades and technical support.

Design Support and Availability

Design support for the EP20K60E and EP20K1500E will be available in upcoming Quartus software in October 1999 and February 2000, respectively. The planned shipment schedules for the EP20K60E, EP20K1500E, and other announced members of the APEX 20KE family are shown in the following table: -0-
 Device                                      Availability
 ---------                                   ------------
 EP20K400E                                   October 1999
 EP20K600E                                   November 1999
 EP20K1000E                                  Q1'00
 EP20K300E                                   Q1'00
 EP20K200E                                   Q1'00
 EP20K100E                                   Q1'00
 EP20K1500E                                  Q2'00
 EP20K160E                                   Q2'00
 EP20K60E                                    Q2'00


Safe Harbor Notice

This press release contains "forward-looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and  of 1995. Forward-looking statements are generally preceded by words such as "expects," "believes," "anticipates," "projects," or "intends." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risks that the Company's products will not satisfy customer demands and may not be available by announced date, that specific densities aren't reached or other companies develop products with higher densities than those offered by the Company. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.

About Altera

Altera Corporation, The Programmable Solutions Company(TM), was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market Nasdaq stock market

The first electronic stock market listing over 5000 companies. The Nasdaq stock market comprises two separate markets, namely the Nasdaq National Market, which trades large, active securities and the Nasdaq Smallcap Market that trades emerging growth companies.
 under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.

Note to Editors: Altera, The Programmable Solutions Company, APEX, System-on-a-Programmable-Chip, MultiCore, Quartus, MAX+PLUS, FineLine BGA, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.
COPYRIGHT 1999 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1999, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Aug 27, 1999
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