Altera Breaks Into High-Performance System Datapath with Introduction of APEX II Family.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--April 23, 2001

Altera Corporation (Nasdaq:ALTR), a leading programmable logic device (PLD) supplier, today announced its APEX(TM) II device family, Altera's next-generation high-performance, high-density PLD family for system-on-a-programmable-chip (SOPC) applications. Building on the successful APEX architecture, the APEX II device family marks a breakthrough in capability and system performance that will for the first time place programmable logic directly in the datapath of high-performance communication applications. The APEX II device family incorporates dramatic enhancements to both the I/O and memory structure. This allows designers to incorporate significantly higher-level system functionality onto a single PLD, delivering the speed, flexibility, and SOPC integration required for areas such as advanced wireless, optical switching and networking technologies.

"The features in the APEX II device family make it the perfect solution for many of our complex applications," said Rich Corley, Pirus Network's founder and executive vice president of technology. "The new differential I/O standards, enhanced memory interface and improved phase locked-loops (PLLs) make the APEX II family a superior solution to other PLD alternatives."

"SOPC devices with high-speed I/O, such as Altera's APEX II family, are bringing the benefits of programmable logic to a new class of applications," said Anne Sanquini, vice president and general manager of Mentor Graphics' HDL Design Division. "Our FPGA Advantage design flow, with capture, simulation, and synthesis, delivers a complete solution to maximize silicon performance on an APEX II device."

The APEX II device family expands Altera's PLD logic capacity to over 89,000 logic elements (LEs) and 1.5 Mbits of on-chip RAM. Designed to optimize system performance across a broad range of high-performance communication applications, allowing system designers to use APEX II devices as their "customization engine" to bridge different communications protocols. APEX II devices can integrate a broad range of communication protocols such as POS-PHY L4, HyperTransport, Utopia L4, Flexbus L4, CSIX, and RapidIO. As a result, family members can interface directly to ASSPs, packet processors, host processors, and other standard functional blocks found in communication systems. This unique ability to address so many of the emerging high-speed I/O protocols allows all of the benefits of SOPC-based design to be realized directly in high-speed datapaths.

"The APEX II devices are all about SOPC, the ability to integrate more and more system-level functionality onto a programmable chip," said Tim Colleran, Altera vice president of product marketing. "The unique capabilities of APEX II devices are opening up the system-level datapath functionality to the benefits of programmable logic for the first time."

Designed for the Datapath

The most significant technological innovation in the APEX II devices is enhanced I/O capability. The APEX II devices support both 1-Gbps True-LVDS(TM) channels (low voltage differential signaling) and 624-Mbps Flexible-LVDS(TM) channels. These channels support the popular LVDS, LVPECL (low-voltage pseudo-emitter-coupled logic), PCML (pseudo current mode logic) and HyperTransport interfaces. The APEX II devices offer up to 124 input and 124 output channels of high-performance differential I/O support. High-performance single-ended I/O standards such as HSTL Class I, II at 250 MHz are also supported and, when combined with the differential I/O capability of APEX II devices, total almost 380 Gbps of total device bandwidth. Finally, the APEX II architecture contains a proprietary technology, clock-data synchronization (CDS), to allow a variety of new, board-level differential clocking topologies. This technology is a significant step forward in increasing system performance and enabling higher chip-to-chip performance with easier board-level design.

Manufactured on TSMC's state-of-the-art 0.15-micron all-layer copper process, the APEX II devices deliver increased logic capacity and performance through a combination of architecture and process technology. On the memory front, the APEX II devices have up to 1.5 Mbit of true dual-port RAM on chip, and the I/O cells are designed to support the fastest leading-edge external memory interfaces such as ZBT SRAM, QDR SRAM, and DDR.

Intellectual Property (IP) Solutions

Currently 135 IP cores are available from Altera and its AMPP(TM) partners in the areas of signal processing, communications, and embedded systems for APEX II devices. High-speed communications interface IP solutions are available such as POS-PHY L4, HyperTransport, and RapidIO that take advantage of the advanced I/O featured in APEX II devices. Additionally, Altera's Nios(TM) core, the industry's first embedded processor soft core, has also been ported to the APEX II architecture, allowing it to take advantage of the unique capabilities of the APEX II family.

Availability, Packaging, and Pricing

The APEX II device family will range in density from 16,640 LEs with over 400 Kbits of on-chip RAM to 89,200 LEs with over 1.5 Mbits of on-chip RAM.

                             Embedded
           Logic Elements    System Blocks      Memory    Differential
Member     (LEs)             (ESBs)             (Kbits)   Channels(a)

EP2A15      16,640              104               416          92
EP2A25      24,320              152               608          92
EP2A40      38,400              160               640         124
EP2A70      67,200              280              1,120        124
EP2A90      89,280              372              1,488        124

      (a) Differential Channels include: LVDS, HyperTransport, PCML,
        LVPECL

Packages are based entirely on BGA technology and will be offered with both 1.27-mm and 1-mm ball spacings. The first device will be the EP2A15, sampling this quarter with a volume price of $150 by mid 2002. Altera's APEX II devices will be supported by the Quartus(TM) II development software, which offers the industry's fastest compile times and highest device performance.

About Altera

Altera, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Safe Harbor

This press release contains "forward-looking statements" that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words that imply a future state such as "expected" or that imply that a particular future event or events will occur such as "will". Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that future performance is dependent on product development schedules, the design performance of software and other tools, as well as the company's and third parties' development technology and manufacture capabilities. Please refer to the company's Securities and Exchange Commission filings, copies of which are available from the company without charge.

Note to Editors: Altera, The Programmable Solutions Company, APEX, True-LVDS, Flexible-LVDS, AMPP, Nios, Quartus, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.