Altera's New IP Cores Expand Leadership in DSP Market.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 21, 2001

IP/SoC Conference

Altera Corporation (Nasdaq:ALTR), a leading supplier of programmable logic devices (PLDs), today announced two new intellectual property (IP) cores that extend Altera's strong presence in the digital signal processing (DSP) marketplace. Altera has the largest portfolio of signal processing IP with over 50 cores that are key enablers for next-generation wireless communication systems, specifically 3G wireless, LMDS (local multipoint distribution system), MMDS (microwave multipoint distribution system), and satellite communications.

"Altera appears to have the largest portfolio of signal processing IP functions for programmable logic, which are the critical blocks for the emerging applications in the wireless, communications infrastructure and broadband markets," said Will Strauss, president and founder of Forward Concepts. "The proven signal processing functions when combined with Altera's leading-edge APEX(TM) 20K family, puts Altera in the forefront to tap into the exploding DSP market."

Historically, DSP applications have been the domain of DSP processors, application-specific integrated circuits (ASICs), or application-specific standard products (ASSPs). Although DSP Processors are flexible, they offer limited real-time performance. ASICs and ASSP devices are capable of real-time processing, but are limited in their adaptability and flexibility. Conversely, DSP functions implemented in programmable logic combine the flexibility that is critical for product differentiation with the speed needed for high-performance applications.

According to Forward Concepts, the use of programmable logic in DSP applications is growing at 37 percent CAGR over the next five years, which is significantly higher than the growth of DSP processors. Overall, the programmable DSP chip market is expected to grow to $20B by 2005, one of the fastest growing markets in the semiconductor industry.

"PLDs, because of their unique parallel processing architecture, continue to see tremendous growth in DSP applications," said Tapan Mehta, Altera IP marketing manager. "With access to our broad signal processing IP portfolio, Altera customers are able to leverage the performance, flexibility, and ease-of-use of Altera's programmable solutions."

Signal Processing IP Addresses Entire DSP Market

The signal processing IP cores are designed for the communications applications that need blistering performance and flexibility. These functions have user-friendly MegaWizard(R) graphical user interface (GUI) offering DSP software engineers an intuitive, flexible environment to customize the IP to meet any system requirements. Each signal processing IP core has been rigorously tested and meets the exacting requirements of IEEE and other communications standards setting bodies. The signal processing IP portfolio consists of Altera's industry-leading forward error correction (FEC) cores such as Reed Solomon, Viterbi, and Turbo, modulation cores such as NCO compiler, encryption cores such as DES, and various other cores such as FIR compiler and FFT.

New IIR Compiler and Constellation Mapper/Demapper IP Cores

Digital filters provide an important function in DSP designs, and are used in a wide variety of applications such as signal separation, restoration, and shaping. The two classes of digital filters are infinite impulse response (IIR) and finite impulse response (FIR). FIR filters are primarily used for high data throughput applications that require a sharp cut-off characteristic. The IIR structure is well suited to automatic gain control circuits (AGC), Goertzel algorithm implementation, digital direct synthesis, or cascaded integrated comb (CIC) filters. The IIR order 2 filter, for industrial control applications, can be implemented in Altera's APEX EP20K30E device for less than $2, providing significant savings versus specialized chips. Altera's IIR Compiler (ordering code: PLSM-IIR) is priced at $7,995.

Constellation mapper/demapper (ordering code: PLSM-SYMMAP) is implemented in modulators/demodulators in virtually all digital band pass communication systems. It is the required building block in all modulator/demodulator systems and can also be found in other applications such as digital video broadcast and 3G wireless communications. The constellation mapper/demapper core can be used to implement a 256 QAM (quadrature amplitude modulation) demodulator in a 3G wireless basestation for less than $2.50 when implemented on an APEX EP20K30E device. Constellation mapper/demapper is priced at $3,995.

Both these cores have been integrated with leading third-party system-level DSP tools such as MathWorks's MATLAB and Simulink, allowing designers to easily model their entire DSP system. Optimized for Altera's APEX, FLEX(R), ACEX(TM), and Mercury(TM) device families, both these cores are available now and can be downloaded from Altera's IP MegaStore website (www.altera.com/IPmegastore).

About Altera

Altera Corporation, The Programmable Solutions Company(R), was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Altera, The Programmable Solutions Company, APEX, MegaWizard, FLEX, ACEX, and Mercury are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.