Alta Group Announces Convergence Simulation Architecture Supporting Full-System, Mixed-Level Verification; New SPW Simulation Technology for Convergence Applications Leverages Berkeley's Ptolemy Project Research.

BOSTON--(BUSINESS WIRE)--Oct. 24, 1995--The Alta Group of Cadence Design Systems today announced at the 1995 DSP World Expo and Conference its CONVERGENCE(TM) Simulation Architecture, a new, state-of-the-art technology foundation for Alta Group's leading electronic system design automation (ESDA) offering, SPW(TM) (Signal Processing WorkSystem(R)). The new CONVERGENCE Simulation Architecture was developed to address two trends in the industry: 1) the convergence of system-level design and chip-level design (due to the evolution towards systems on a chip), and 2) the convergence of communications and multimedia application domains.

The CONVERGENCE Simulation Architecture enables, for the first time, full-system, mixed-level and mixed-domain simulation, enabling continuous analysis and verification of the increasingly complex convergence designs from concept to implementation. Users will benefit by dramatically increased confidence in first-time systems success and dramatically shorter, more predictable design cycles (with fewer iterations).

The new simulation architecture is based on research from the renowned Ptolemy research project at the University of California at Berkeley. The Ptolemy research project, which began in January 1990, is a system-level design framework that allows mixing of multiple models of computation. Alta Group consulted with Dr. Edward A. Lee, professor at U. C. Berkeley's College of Engineering and director of the Ptolemy project, and utilized the Ptolemy team's results to uniquely implement Ptolemy's advanced simulation algorithms in Alta Group's leading SPW solution.

The Convergence Paradigm

The convergence of system-level design and chip-level design and the convergence of communications and multimedia are generating a new class of systems on a chip and complex boards that merge these various "convergence" functions, each of which requires multiple, interacting modeling paradigms. An example of such a system is a set-top box, which merges wired communications functions, wireless communications functions and multimedia processing. These types of consumer-oriented convergence applications are merging data, speech, image processing and control functions, which are implemented with a combination of hardware and software on very complex chips. Thus, a heterogeneous simulation architecture is required to verify the convergence designs at multiple abstraction levels for multiple interacting domains of the design. Previously, designers were only able to effectively model and simulate isolated system functions and were limited in their ability to effectively mix system and chip levels of abstraction.

"The technology breakthrough in the area of mixed-level simulation algorithms has enabled Alta Group to deliver the first step in realizing full-system, multi-level simulation," said Dr. Lee. "As the complexity of designs increases, so does the need to validate designs at multiple levels of abstraction. This requires that simulations interact across levels. The new algorithms and technology that were developed in the Ptolemy project and applied by Alta Group will pave the way for continued advancements in the area of heterogeneous system simulation."

According to Baruch Deutsch, director of product marketing, Alta Group, "The CONVERGENCE Simulation Architecture represents a significant milestone on Alta Group's multi-year technology roadmap. This new technology foundation positions Alta Group for another decade of leadership in systems and systems-on-a-chip design in the highest growth convergence applications."

CONVERGENCE Simulation Architecture Features

The CONVERGENCE Simulation Architecture is a key component of Alta Group's new SPW version 3.5. Enhanced features of the SPW 3.5 solution, enabled by the CONVERGENCE Simulation Architecture, include:

-- control and dataflow modeling

-- synchronous and dynamic dataflow modeling

-- limited precision and clocked domain modeling

-- hardware and software modeling

-- VHDL and Verilog co-simulation

-- network environment modeling

The CONVERGENCE Simulation Architecture supports new, powerful capabilities for modeling control-oriented functions and the interactions with data, voice, or image processing functions. By combining a new entry method, a graphical finite state machine (FSM) editor, along with the existing block diagram editor (BDE) and the new CONVERGENCE Simulation Architecture as a foundation, designers can, for the first time, capture and simulate critical control and dataflow interactions of the design from algorithmic through clocked micro-architectural levels. In addition, the technology now supports object-oriented modeling capabilities to support the effective management of mixed-level representations (such as data types) across levels of abstractions and design domains. The combination of these capabilities allows users to improve their analysis and optimization capabilities, productivity during the refinement process, and confidence in verification. FSM descriptions can be converted into C, Verilog or VHDL.

Within the dataflow modeling paradigm, the CONVERGENCE Simulation Architecture uniquely supports a combination of synchronous dataflow (SDF) models and dynamic dataflow (DDF) models. DDF is applicable to the general case of variable-rate signal processing systems, which has evolved to be a critical element in today's communications applications. SDF is applicable to fixed-rate signal processing and can take advantage of "static scheduling" techniques, which offer significant simulation performance advantages.

As the design is refined, the CONVERGENCE Simulation Architecture uniquely supports built-in, fixed-point attributes to rapidly model limited precision effects and a new, upgraded modeling foundation for mixing in detailed micro-architecture and processor models. To support these detailed models, the CONVERGENCE Simulation Architecture supports the modeling of multiple clocks, asynchronous resets and gated clocks, all of which are critical for real-world hardware and cycle- and phase-accurate processor modeling. To provide interoperability with HDL environments, the CONVERGENCE Simulation Architecture also supports interfaces to leading VHDL and Verilog simulators. The ability to mix algorithm, limited precision and real-world clocked models in a single simulation environment is unique in the industry and critical to ensure that hardware and software architectures are verified in the context of the target system and complex environment.

Finally, the CONVERGENCE Simulation Architecture supports a co- simulation link to Alta Group's BONeS(R) DESIGNER(TM) product, the industry-leading, block-oriented network simulator that is particularly useful for modeling the network environment that new convergence designs must operate in. The combination of SPW, with the CONVERGENCE Simulation Architecture, and BONeS allows users to model a complete system, including the components to be designed (e.g., set-top box or cellular phone), and the network at both the physical and network layers.

Pricing and Availability

The CONVERGENCE Simulation Architecture is available in beta shipments now as the core of Alta Group's SPW 3.5 release, with commercial shipments scheduled for January 1996 at $25k per seat in the United States (node locked); the finite state machine is priced at $10k per seat in the United States (node locked); the BONeS/SPW 3.5 link is included in the respective packages.

Alta Group is the leading supplier of system-level software tools, libraries and services for the design electronics systems. The company's products are focused on the early, high-level portion of the design cycle where fundamental design decisions are made. Products of this type are classified as electronic system design automation (ESDA). Alta Group's target customers include electronic systems and semiconductor companies that design wireless communications, multimedia and networking products. -0-

Note to Editors: Alta Group, SPW, DESIGNER and CONVERGENCE are trademarks of Alta Group. The Signal Processing WorkSystem and BONeS are registered trademarks of Alta Group. All other trademarks or registered trademarks are the property of their respective owners.

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