Alliance Introduces DDR Support Solutions for JEDEC Memory Modules; Full JEDEC Compliant Support Silicon for Buffered / Registered DIMM's.

SANTA CLARA, Calif. -- Alliance Semiconductor Corporation (NASDAQ: ALSC), a worldwide provider of Analog and Mixed Signal products, High-performance Memory products, Connectivity and Networking solutions for the communications, computing, embedded, industrial and consumer markets, announced today, the availability of its JEDEC DDR I Series of fully compliant JEDEC buffered/registered DIMM support silicon.

Alliance's JEDEC DDR I Series consists of 4 devices today; the ASM5CVF857, a PLL based zero delay buffer, and three register variations in concert with the JEDEC JC40/JC45 DDR I 400 specifications; the ASM4SSTVF16857, (14 bit 1:1), the ASM4SSTVF16859 (13/26 bit 1:2), and the ASM4SSTVF32852 (24/48 bit 1:2). Designed specifically to meet and exceed the JEDEC JC40 component standards, these devices support the full mix of JEDEC defined raw cards (PCBs).

Fully compliant to the JEDEC standards, this JEDEC DDR I Series features improved waveform integrity and accuracies yielding better overall timing margins for the RDIMM designer. The JEDEC standards provide the basis for a solid design, and maximum timing margins can be realized using Alliance's JEDEC DDR I Series. Improvements in overall accuracy with respect to jitter, duty cycle and Tr/Tf, combine to provide the basis for timing margin optimization. The JEDEC DDR I Series is offered in the full compliment of package options to include all the JEDEC defined PCB configurations supporting: 48 and/or 64TSSOP, 48TVSOP, 40 and 56QFN, VQFN, 56PBGA and 114LFBGA.

"We are very pleased to augment our analog and mixed signal product portfolio with the introduction of the JEDEC DDR I Series," said Mark Sherwood, Director of Marketing for Alliance's Mixed Signal Business Unit. "This series offer the designers of DIMM modules compatibility with existing solutions on the market and improved timing margins. Alliance is an active participant member of the JEDEC JC40, JC45 and other associated committees, helping both to create and to drive these standards."

Alliance's JEDEC DDR I Series is fabricated using state-of-the-art low voltage 2.5V CMOS designs and process, and supports performance through the current DDR 400 (200MHz) standards.

The JEDEC DDR I Series includes a PLL based Zero Delay Buffer (ZDB) with differential SSTL II class II outputs. The full Series is currently in full volume production. Additional information and full data sheet specifications are available via the Alliance Semiconductor website at http://www.alsc.com/products/ddr.htm

About Alliance:

Alliance Semiconductor Corporation (NASDAQ: ALSC) is powering every application with high performance solutions for the communications, computing and consumer electronics markets. Utilizing advanced process technologies and design expertise, Alliance provides leading OEMs with a broad portfolio of complementary technologies including analog and mixed-signal products, chip-to-chip connectivity products, networking controllers and high-performance memories. Alliance addresses the complete needs of system developers by leveraging its proprietary advances in Electromagnetic Interference (EMI) reduction, power management and timing technology, HyperTransport(TM) I/O connectivity and specialized memory solutions for next-generation applications. Founded in 1985, Alliance is headquartered in Santa Clara, California with design centers in Bangalore and Hyderabad, India. The company is publicly traded and included in the S&P 600 Index. Additional information is available on the Alliance Web site at: http://www.alsc.com.