Align Lock Loop Breakthrough Ensures Single-Clock Domain.

FRIDAY HARBOR, Wash. -- Startup Align Engineering came out of stealth mode today, announcing a technology breakthrough that is the basis for fast, simple chip-to-chip communication without multiple IO lines and intensive engineering. The patented technology, called Align Lock Loop (ALL), provides for a cost-effective alternative to today's complex SerDes IO designs.

ALL technology enables each LVDS pair to morph into a complete SerDes solution in a single clock domain, eliminating the need for multiple expensive clock data recovery devices (CDRs) and associated phase lock loops (PLLs). ALL gives designers the ability to achieve simple high-speed connectivity for such applications as wireless infrastructure, medical imaging, military and defense.

"With ALL, boards in racks will give way to clusters of boards with digital communication, cabling to analog data sources, saving substantial cost and providing higher performance," said Jerry Hinson, Engineering Specialist at Applied Signal Technology.

"Align Lock Loops are ideal for high-speed applications where they eliminate expensive CDRs and alignment complexity," said Align Engineering founder and CEO Bryan Hoyer. "Creating a single-clock environment has a positive impact on initial design simulation, cost, and simplicity. It is also offers a substantial improvement in interoperability and time to market," Hoyer added.

About Align Engineering

Align Engineering develops advanced and cost-effective alternatives to today's challenging SerDes IO designs that demand complicated PLLs and CDRs. Align enables rapid design, the elimination of expensive components, and unprecedented implementation simplicity, all within a single-clock methodology.