Aldec and Synplicity(R) Partner on Encrypted IP Flow; New Release of Riviera 2006.06 Supports Open IP Encryption Initiative.

HENDERSON, Nev. -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announces support for the Open IP Encryption Initiative design flow in the latest version of Aldec's Riviera tool. The Open IP Encryption Initiative is a non-proprietary IP encryption methodology authored by Synplicity(R), Inc, (Nasdaq:SYNP), a leading supplier of innovative synthesis, verification, and DSP implementation software solutions for FPGA designers. Synplicity has worked with Aldec to support this new methodology of handling IP (Intellectual Property) encryption in simulation and synthesis. E[acute accent]Lack of an industry-wide standard for IP encryption and decryption has concerned both IP vendors and their customers for a long period of time. While easy to use, unencrypted IP cores were prohibitively expensive for some customers, and availability of cheaper (but encrypted) versions working with customer tools was spotty. Maintaining multiple IP core versions for multiple tools was also cumbersome for IP vendors. With built-in support for the new Open IP Encryption flow, engineers can easily compile, simulate and synthesize, Verilog encrypted IP with Synplicity's Synplify(R) and Synplify Pro(R) FPGA synthesis software and Aldec's Riviera tools. E[acute accent]"Aldec's support for the Open IP Encryption Initiative will help to create a front-to-back design capability with comprehensive encrypted IP support," said Andy Haines, senior vice president of marketing at Synplicity. "Users of Aldec's Riviera product will be amongst the first to benefit from a truly open and easy-to-implement IP protection scheme where all tools will be able to analyze and optimize the IP source code in the same way as unencrypted source code."

E[acute accent]Simulating Encrypted Verilog Sources

E[acute accent]Simulation of encrypted Verilog sources based on Synplicity's Open IP Encryption Initiative methodology is now available in the new release of Aldec's Riviera 2006.06 high performance SoC simulator. The flow is compatible with the recently published Verilog standard IEEE Std 1364-2005 and forthcoming VHDL 2006 standard. It enables easy encryption of any fragments of IP cores for secure delivery from the IP vendor to the customer. The encryption involves no action on the side of the customer -- all required activities involve IP vendor and tool vendors only. Customers can open delivered IP source but will only see unintelligible, encrypted and encoded text. The Riviera compiler will be able to decrypt the source on-the-fly, leaving no traces that could compromise the security of encryption.

E[acute accent]Additional Improvements in the Riviera 2006.06 Release

E[acute accent]Additional improvements in Riviera 2006.06 include faster Verilog and VHDL compilation and simulation; PSL assertions embedded in VHDL code for improved verification, communication and IP correct usage detection; Expression Coverage for fine grained statistics analysis of testbench effectiveness; and numerous GUI enhancements.

E[acute accent]About Synplicity's Open IP Encryption Initiative

E[acute accent]Information about the Open IP Encryption Initiative is available at www.synplicity.com, including a white paper with detailed information on the flow. To foster industry discussion on this flow, Synplicity will host a panel discussion during the Design Automation Conference entitled, "An Industry Standard IP Protection System for EDA Tool Flows" moderated by Gabe Moretti, Gabe on EDA. The panel session will be held on Tuesday, July 25, 2006 from 7:30 to 9:15 a.m. in Room 302 of the Moscone Center. The panel session is open to all DAC attendees. To register for DAC 2006 visit www.dac.com.

E[acute accent]About Riviera

E[acute accent]Riviera, a high-performance verification tool, is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology and is used by ASIC and high-density FPGA designers for new generation system-on-chip designs. It supports IEEE VHDL 1076-87/93 and VITAL 2000 in addition to Verilog 1364-2001 and SystemVerilog. Code coverage, Waveform Viewer, advanced dataflow, Design Profiler and interfaces to other EDA tools are provided via PLI and VHPI function calls as part of Riviera's product configuration.

E[acute accent]About Aldec

E[acute accent]Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX(R), Linux(R) and Windows(R) platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service are the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.

E[acute accent]Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.