Aldec and Synopsys Partner to Offer Time-Based FPGA Design Solution.

Business Editors & High-Tech Writers

HENDERSON, Nev.--(BUSINESS WIRE)--Aug. 14, 2000

Active-HDL(TM) Express Features a Fully Integrated VHDL, Verilog or

Mixed Simulation and Synthesis Solution for all FPGA Devices

Aldec Inc., a leading supplier of HDL design entry and verification software for programmable logic devices, today announced a strategic partnership with Synopsys(R) Inc. (Nasdaq:SNPS) to bundle Synopsys' FPGA Express(TM) synthesis solution with Aldec's Active-HDL design entry and verification environment.

The combined product is offered under the new product name, Active-HDL Express, and provides a complete solution for VHDL, Verilog and mixed VHDL, Verilog and EDIF based designs. The new product delivers unparalleled integration, creating a solution with both ease of use and complete control of projects from design entry through RTL simulation to logic synthesis for all programmable logic vendors. Active-HDL Express is available in perpetual and annual time-based licensing.

"FPGA designers are confronted with rapidly changing design requirements and shorter time-to-market demands," stated Stanley Hyduke, chief executive officer of Aldec. "Our partnership with Synopsys allows Aldec to deliver a completely integrated `best-in-class' FPGA design environment for all leading FPGA vendors."

"Aldec's integrated environment, together with Synopsys' technology leadership in FPGA Express, delivers a comprehensive solution for FPGA designers," offered Jay Michlin, vice president and general manager of Synopsys' FPGA group. "With full FPGA vendor support, and compatibility with advanced ASIC design flows, Active-HDL Express gives designers flexibility to choose the right device for their critical projects in today's dynamic environment."

Impact on the Industry

Active-HDL Express offers more flexibility and features than other design solutions. It is a complete FPGA design environment that supports all programmable logic technologies and provides unrestricted performance for mixed VHDL, Verilog and EDIF designs. Synopsys' FPGA Express is the only synthesis technology that is resold by both leading programmable logic vendors, Altera(R) and Xilinx(R). This provides their customers with synthesis solutions that are unique to their specific devices.

The bundling of FPGA Express with Active-HDL gives designers the highest-quality logic synthesis software and a complete HDL-centric design environment that supports all FPGA devices, providing designers the freedom to target the device that best suits their design.

Time-Based Licensing

Active-HDL Express is the first integrated solution to be offered with a time-based licensing option that allows users to take advantage of all the advanced technology at an annual renewal rate. This benefits designers with a lower cost of entry, free product updates and the same access to product support as users with maintenance contracts from perpetual licenses.

Active-HDL Express Features

-- HDL, State Machine and Block Diagram Editors

-- Tcl / Tk Scripting

-- Automated FPGA Design Flow

-- Code2Graphics(TM)

-- Automatic Testbench Generation

-- Graphical Waveform Viewer / Editor

-- VHDL, Verilog, or mixed VHDL/Verilog and EDIF simulation and

logic synthesis

-- Block Level Incremental Synthesis (BLIS)

-- Architecture-specific optimization and mapping for leading

programmable logic vendors

-- TimeTracker(TM), integrated static timing analyzer and viewer

Upgrade path to ASIC design flows

Design Flow

The design flow for Active-HDL Express is simple and intuitive. Designers can use a single tool for design entry, simulation and push-button synthesis. The only additional software required to complete the design flow is the place and route software from the targeted programmable logic vendor. Active-HDL Express also offers a path to ASIC design flows via the upgrade option to Synopsys Design Compiler(TM) and FPGA Compiler II(TM).

Availability

Active-HDL Express is available today and sold exclusively by Aldec Inc. The product is available as either a permanent or time-based license and includes HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram/Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, choice of a VHDL, Verilog or mixed VHDL, Verilog and EDIF simulation and Synopsys FPGA Express logic synthesis.

The first year of maintenance for all perpetual licenses is included. All time-based licenses are issued for a period of 12 months, and a 50% credit can be applied toward a perpetual license if purchased within the first year. To receive your free evaluation copy of Active-HDL Express, contact Aldec at www.aldec.com.

Active-HDL    VHDL     Verilog     Mixed    Time-Based    Permanent
 Express   Simulation Simulation Simulation   License      License
                                                Node    Node    Float
  Dual
Language       X          X          X         $7,500 $17,500 $21,500

 Verilog                  X                    $5,000 $12,000 $16,000

  VHDL         X                               $5,000 $12,000 $16,000

About Synopsys

Synopsys Inc., with headquarters in Mountain View, Calif., creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

About Aldec

Aldec has offered PC-based design entry and simulation solutions to FPGA designers for more than 15 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx Inc. (Nasdaq:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, with headquarters in Henderson, produces a universal suite of Windows-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL).

Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest-growing privately held EDA supplier in the world. Additional information about Aldec is available at http://www.aldec.com.

Note to Editors: Active-HDL and Active-CAD are trademarks of Aldec Inc. All other trademarks or registered trademarks are property of their respective owners.