Aldec and Celoxica Release Mixed HDL- AND C- Language Design Environment for FPGA Developers; Partnership Focuses on Needs of High-Density FPGA Users.

Business Editors/High-Tech Writers

CAMPBELL, Calif. & HENDERSON, Nev.--(BUSINESS WIRE)--Nov. 4, 2003

Celoxica, Ltd. and Aldec, Inc. today announced the availability of Active-HDL+C, an integrated FPGA design environment that combines Aldec's Active-HDL design entry and mixed-HDL simulation technology with Celoxica's DK engine for C-synthesis and co-simulation.

The combined Active-HDL+C package offers FPGA designers the productivity gains of mixing HDL with Handel-C from one integrated environment. The designer is not required to learn multiple design entry and verification tools; therefore, design creation, project management, documentation, HDL simulation, co-simulation (HDL and C), C-synthesis as well as interfaces to third party FPGA place and route tools are controlled within a single flow.

Active-HDL+C provides a comprehensive FPGA design environment that supports both traditional RTL as well as emerging C-based flows. It offers block-based design entry for VHDL, Verilog and Handel-C, and performs co-simulation of these blocks on a single screen. By integrating Celoxica's C-synthesis and co-simulation technology with Active-HDL, users can simulate C with HDL and compile software algorithms directly into device-optimized FPGA hardware. The package completes the design flow with timing simulation (EDIF Netlist or HDL netlist with SDF).

The Active-HDL+C package is now available through both Aldec and Celoxica sales channels worldwide.

The complete version of this press release, including design flow diagram, can be located at: URL: http://www.aldec.com/Press/Releases/?ID=235&year=2003. Additional information about the integration and application note will be at: http://www.aldec.com/ActiveHDL/celoxica.htm