Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design.HENDERSON, Nev. & MOUNTAIN VIEW, Calif. -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices, today announced the release of CoVer[TM], a Windows[R]-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL ACTL American College of Trial Lawyers (Irvine, California) ACTL Access Carrier Terminal Location ACTL Activation Library ACTL Automated Compatibility Test Laboratory ACTL Association Cultural Turkey-Luxembourg ). Easing hardware and software integration for engineers using Actel's field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel's CoreMP7 soft ARM7[TM] core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs. "CoVer is the only product on the market offering hardware-accelerated HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers," stated Dr. Stanley Hyduke, president of Aldec, Inc. "This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB (programming, tool) GDB - GNU debugger. The FSF's source-level debugger for C, C++ and other languages. Developed by many people but most recently Fred Fish <fnf@cygnus.com>, Stu Grossman <grossman@cygnus.com> and John Gilmore <gnu@cygnus. debugger." Jake Chuang, senior director, application solutions marketing at Actel, said, "As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec's innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk." System Performance Utilizing Aldec's patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator oscillator Mechanical or electronic device that produces a back-and-forth periodic motion. A pendulum is a simple mechanical oscillator that swings with a constant amplitude, requiring the addition of energy at each swing only to compensate for the energy lost because of air generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions. Hardware in-the-loop The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel's ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec's patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). or JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group , the reusable CoVer board can be used for any CoreMP7-based embedded design. Components The CoVer solution provides engineers with a complete HW/SW HW/SW Hardware/Software co-verification toolset: * Aldec Active-HDL (Designer Edition) mixed-language simulator * Actel's CoreConsole IP Deployment Platform * Actel Libero Libero can refer to:
* Reusable FPGA-based prototyping board with Actel's ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core * Software development system, including Actel's SoftConsole program development environment Availability CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com. About Aldec Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). , Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com. About Actel Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. |
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