Aldec Selected by Thales to Deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System.HENDERSON, Nev. -- Aldec, Inc. announced today that Thales has decided to deploy the DO-254/ED-80 CTS (1) (Clear To Send) The RS-232 signal sent from the receiving station to the transmitting station that indicates it is ready to accept data. Contrast with RTS. (2) (Common Type System) The data typing used in . (Compliance Tool Set) from Aldec. The DO-254/ED-80 CTS is an In-Hardware FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. validation system developed to meet Level A-D A-D Advance-Decline, or measurement of the number of issues trading above their previous closing prices less the number trading below their previous closing prices over a particular period. requirements defined by the DO-254/ED-80 Design Assurance Guidance for Airborne Electronic Certification Manual. The deployment of the system has enabled Thales to validate for the certification authorities that the hardware implementation of an advanced avionics system's RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; design is working correctly at the required speed in the targeted FPGA. "Our project involved an Altera Cyclone[R] II FPGA with multiple clocks and speeds in excess of 128MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. . We wanted a complete verification path with requirements traceability Overview Traceability as a general term is the "ability to chronologically interrelate the uniquely identifiable entities in a way that matters." The word chronology and simulation results maintenance to validate that our system would work on the final hardware we deliver to our customer," said Eric Cardone, program manager at Thales Land & Joint Systems Division. "Aldec's DO-254/ED-80 CTS gave us an effective way to meet the Level B Verification process requirements imposed by the DO-254 certification authorities." "Specifying a complete test strategy to verify each of the system requirements To be used efficiently, all computer software needs certain hardware components or other software resources to be present on a computer system. These pre-requisites are known as (computer) system requirements and are often used as a guideline as opposed to an absolute rule. is a very important part of the DO-254/ED-80 certification process," said Dr. Stanley Hyduke, president of Aldec. "The Thales engineering team used our DO-254/ED-80 CTS solution to verify that each requirement of the safety critical system was met on the end-target hardware, as it is required by Chapter 6.2 Verification Process of the DO-254/ED-80 specification. The solution was able to identify problems in the design and provide DO-254/ED-80 certification authorities the verification data required for Level B compliance." "As worldwide enforcement of the DO-254 standard grows, Thales has taken a leadership role in the avionics industry by adopting the standard within its airborne electronic hardware systems," said Amr El-Ashmawi, senior business unit manager, military and aerospace, at Altera. "Aldec's DO-254/ED-80 CTS In-Hardware FPGA validation system, along with Altera's design flow and Cyclone II FPGAs, allow Thales to have an end-to-end solution (jargon) end-to-end solution - (E2ES) A term that suggests that the supplier of an application program or system will provide all the hardware and/or software components and resouces to meet the customer's requirement and no other supplier need be involved. Compare: turn-key solution. that addresses DO-254 certification requirements. Altera and its DO-254 Global Partner Network, including Aldec, recognize the importance of providing companies like Thales a comprehensive DO-254 environment which will save them a significant amount of engineering time and development costs." Thales Usage Model Aldec's DO-254/ED-80 CTS enabled Thales engineers to uncover and resolve design problems that were not visible using an event-driven HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. software simulator. Aldec's DO-254/ED-80 CTS utilized the actual end-target FPGA device and enabled the reuse of the same test vectors as for RTL simulation in order to validate that the designs operation in the final target hardware met the actual system speed requirements without the need for additional analysis as is the case with other verification solutions or prototyping. Utilizing the same test vectors for each stage of the design verification, Aldec's DO-254/ED-80 CTS delivered time savings for requirements traceability and results analysis. The results from each of the tests were stored and documented to be used in the certification process as required by the DO-254/ED-80 Certification Manual. Furthermore, Aldec provided a full set of the tool tests for the qualification process according to according to prep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. DO-254/ED-80 specification. DO-254/ED-80 Compliance Tool Set The DO-254/ED-80 CTS solution from Aldec provides support for Levels A through D of the "Design Assurance Guidance for Airborne Electronic Hardware" (DO-254/ED-80) Chapter 6.2 "Verification Process" and Chapter 11.4 "Tool Assessment and Qualification Process." The DO-254/ED-80 CTS consists of a mixed language HDL Simulation tool suite and In-Hardware Simulation system that supports the customer's specific FPGA, PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. , or ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. target device providing functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and/or at-speed testing. The verification flow requires the design first be checked in the HDL simulator to validate design's functionality against requirements and then in the end-target FPGA hardware. A golden set of waveform vectors validated in the HDL simulation are automatically compared with the set of waveform vectors generated after in-hardware simulation in the end-target FPGA device. In-hardware testing provides assurance that the design works in the target device just as it did during HDL simulation, with full traceability of the hardware outputs back to the design requirements. Independent Tool Assessment In addition, In-Hardware testing provides independent assessment of outputs from logic synthesis, FPGA vendor place-and-route, and HDL simulation and code coverage tools, fulfilling the DO-254/ED-80 requirements for Level A and B certification requirements. About Altera Altera Corporation (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : ALTR) programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com. About Aldec Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. www.aldec.com Aldec is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. |
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