Aldec Releases Riviera-PRO(TM)2008.06 HDL Simulator.Release Includes New Assertions Waveform Viewer and Seamless Debugging of SystemC/C++ and HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. HENDERSON, Nev. -- Aldec, Inc. announced today the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. designs. Riviera-PRO 2008.06 includes Verilog[R] simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment, and new support for SVA SVA School of Visual Arts SVA Severe (Thunderstorm) Advisory SVA Statens Veterinärmedicinska Anstalt (National Veterinary Institute, Sweden) SVA Shareholder Value Added and PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. assertions in the Waveform Viewer. Riviera-PRO supports System Level Verification with SystemC and SystemVerilog, Assertions based verification, Open Verification Methodology (OVM), Electronic System Level (ESL), and STARC STARC Semiconductor Technology Academic Research Center (Japan) STARC State Area Command STARC Student Alliance to Reform Corporations STARC Somerset Tackling Alcohol Related Crime STARC St. Albans Amateur Radio Club (St. [R] based Linting. Verilog Simulation Performance Speed-Up Verilog simulation speed at the gate level has been increased up to 2.3X over the previous release. Memory allocation during simulation has been significantly reduced to enable larger solutions on 32- and 64-bit platforms. All mixed language designs will benefit from Verilog performance enhancements. SystemVerilog Support Aldec Riviera-PRO 2008.06 supports IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1800TM SystemVerilog, a unified hardware description and verification language. The tool provides support for SystemVerilog design and verification constructs, incorporating enhanced string support, class inheritance, packages, DPI and libraries. Seamless Debugging of SystemC/C/C++ and HDL Ideal for Electronic System Level (ESL) designers, Riviera-PRO offers a new level of integration, enabling SystemC/C/C++ and HDL co-debugging in one simulation environment. Riviera-PRO includes identical procedures for tracing source code, setting breakpoints, viewing objects, and more - no matter what language was used to describe the given portion of the system. New Assertions Support in Waveform Viewer The Riviera-PRO interface dramatically increases visibility of assertions and coverage points, enabling their direct, graphical display in a Waveform Viewer and more detailed statistics in enhanced Assertion and Cover Viewers. Assertion-based verification is enabled throughout the Riviera-PRO product. VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. 200x Support Riviera-PRO provides support for the most recent version of the VHDL4.2, IEEE 1076 2008 standard. Riviera-PRO products will include VHDL 200x Standard and IEEE 1076[TM] 2008. About Riviera-PRO Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC, C/C++, Assertions and EDIF EDIF - Electronic Design Interchange Format. Not a programming language, but a format to simplify data transfer between CAD/CAE systems. LISP-like syntax. See also Berkeley EDIF200. E-mail: <edif-support@cs.man.ac.uk> ftp://edif.cs.man.ac.uk/pub/edif. . Riviera-PRO works in command line mode for maximum speed or in state-of-the-art GUI for enhanced editing, tracing, and debugging capabilities, including code coverage and linting. Riviera-PRO is compatible with industry standards and interfaces with popular EDA products such as Synopsys[R] SmartModels[TM], Novas[TM], Denali[R], MATLAB (MATrix LABoratory) A programming language for technical computing from The MathWorks, Natick, MA (www.mathworks.com). Used for a wide variety of scientific and engineering calculations, especially for automatic control and signal processing, MATLAB runs on Windows, Mac and [R] and Simulink[R]. Pricing and Availability Riviera-PRO 2008.06 is available today. For a FREE evaluation copy of Riviera-PRO 2008.06, please visit http://www.aldec.com/Downloads/default.aspx. About Aldec Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. www.aldec.com Riviera-PRO is a trademark of Aldec, Inc. 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