Aldec Releases Active-HDL 7.3 and Introduces Multi-Threaded HDL Compilation.HENDERSON, Nev. -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices, announced today the release of Active-HDL 7.3. The release includes multi-threaded HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. compilation, new waveform The shape of a signal. See wavelength, sine wave and square wave. viewer and expanded VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. 2006 construct support. A noticeable performance improvement in VHDL, Verilog and mixed RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; compilation and simulation is included as part of the release. Active-HDL is a mixed-language design creation, FPGA Project Management and simulation environment supporting VHDL, Verilog, SystemVerilog, and SystemC. Multi-threaded VHDL Compilation Aldec has implemented multi-threaded compilation for VHDL designs. If Active-HDL 7.3 is installed on machines with multi-core CPUs, the compilation process can be up to 3 times faster. The compilation time of source files based on single processor has been reduced by 40% on average in comparison to the previous version of Active-HDL. New Advanced Waveform Viewer In addition to the Standard Waveform Viewer/Editor, Active-HDL 7.3 now offers the full integration of a new and high-performance Accelerated Waveform Viewer. The new high performance waveform viewer is backward compatible Refers to hardware or software that is compatible with earlier versions of the product. Also called "downward compatible." Contrast with forward compatible. backward compatible - backward compatibility and enables opening, zooming, scrolling, viewing and management of large files (4GB and larger) almost instantaneously. Active-HDL 7.3 can read and write from the waveform database up to 4x faster then previous releases, while decreasing system memory requirements and file size. Signals, including Verilog memories or large VHDL records can be expanded without delay. The new waveform viewer is optimized to support all design sizes and long simulation runs making it ideal for designers utilizing the largest devices from Altera Stratix[R] III and Xilinx Virtex[TM] 5. VHDL 2002 and 2006 Support Active-HDL 7.3 includes enhanced support for VHDL 2002 and 2006 constructs and now supports protected types introduced in the 2002 revision of the VHDL standard (IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. Std 1076-2002[TM]). The VHDL compiler can now compile source files containing protected envelopes, file types and aliases inside VHDL 2002 protected types. Availability Active-HDL is available in four Product Configurations - Desktop Master (DM), Designer Edition (DE), Plus Edition (PE) and Expert Edition (EE). The software is available in floating or node-locked configurations. Active-HDL 7.3, is available today and is sold directly from Aldec and its authorized world-wide distributors. Download a FREE evaluation copy of Active-HDL 7.3 today. About Aldec Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). , Linux, Solaris and Windows platforms. http://www.aldec.com. Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. |
|
||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion