Aldec Releases 64-Bit Mixed HDL Simulator.HENDERSON, Nev. -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices, announced today the release of Riviera 2007.02, a 64-bit mixed-language design simulation environment handling VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , Verilog, SystemVerilog, and SystemC designs. Riviera delivers industry proven simulation performance and accuracy for all multi-million gate HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. designs. "Aldec continues to gain momentum in the ASIC verification market and with the introduction of Altera Stratix[R] III and Xilinx Virtex[R]5 there is a requirement for 64-bit processing and very large amounts of memory to process the designs. Our customers have requested design simulation support based on 64-bit architecture," stated Dr. Stanley Hyduke, President of Aldec, adding, "We responded with Riviera, a 64-bit simulator that supports mixed HDL simulation and debugging, enabling our customers to have continued success in validation of their large IC devices." The densities of ASIC and new FPGA devices demand design verification flows that can utilize the latest multi-core 64-bit processor machines. Riviera, running in a true 64-bit mode, leverages the hardware to perform large simulation runs requiring 16 gigabytes of memory. To further reinforce a designer's control over the quality and speed of design verification, Riviera 2007.02 includes performance optimization for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; and gate level simulation (1.5-2x speed improvements over the previous release), VHDL and Verilog expression coverage, mixed PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. assertion with VHDL and Verilog design blocks support, and graphical debugging tools designed specifically for large IC designs. Pricing and Availability Riviera 2007.02 is available today and is sold directly from Aldec and its authorized world-wide distributors. For a FREE evaluation copy of Riviera 2007.02, please visit www.aldec.com/products/riviera. About Aldec Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). , Linux, Solaris and Windows platforms. Additional information on Aldec and all products can be found at www.aldec.com. Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. |
|
||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion