Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1.

HENDERSON, Nev. -- Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a first-to-market FPGA simulator supporting assertions and functional coverage in SVA, PSL and OVA at an affordable price. Other improvements in this release include Verilog[R] simulation performance speed-up and support for additional VHDL 2008 language constructs. Active-HDL is a mixed-language HDL simulator that offers project management, graphical design creation and support for all leading FPGA vendors from a single integrated design environment.

Property-based Verification

Rapidly growing complexity of FPGA designs makes the introduction of property-based verification an important step to the support of assertions and functional coverage in Active-HDL 8.1. Design properties can be expressed in OVA, PSL or SystemVerilog languages and used in assertions or cover statements, placed directly in the HDL code of the design or in separate verification blocks.

Assertions and Functional Coverage

Assertions monitor behavior of the design and raise an alert when something undesired happens. Functional coverage ensures that all critical behaviors of the design were properly verified. Together they work as self-running safeguards, allowing designers to concentrate on creating a hardware description that simulates and synthesizes as expected. In addition to standard assert/cover messages printed to the console during simulation, Active-HDL enables numerous additional debugging features. Live status of assertions and covers can be viewed in the Hierarchy Browser and a dedicated Assertion Viewer, while global statistics of their execution are available in the Coverage Viewer. Breakpoints can be set on assertion activation, passing or failure events. The HDL Editor supports syntax highlighting for assertions and covers, and the updated Language Assistant makes adding them to the code much easier.

Verilog Simulation Speed-up

Verilog simulation speed at the gate level has been increased up to 2.3X over the previous releases by using the advanced optimization settings available within the simulator. All mixed-language designs will benefit from Verilog performance enhancements.

Additional New Features

Active-HDL 8.1 includes enhanced support for VHDL 2008 (IEEE Standard P1076-2008) including new constructs and libraries. A new DPI-wizard to help create quick interfaces between SystemVerilog and C applications is now included in Active-HDL 8.1. The DPI-wizard allows simple entry of C/C++ tasks and functions and generates C wrappers, and sample SystemVerilog files. The wizard also creates a configuration file for compiling generated C files into a dynamic-link library. Active-HDL 8.1 supports new and updated libraries including: Assertions, OVL 2.2 and VTL.

About Active-HDL

Active-HDL is an integrated FPGA design and verification environment with a powerful mixed-language simulator and tools for graphical design entry, project management, HDL verification and documentation, providing an efficient (FPGA vendor-independent) environment for end-to-end design processing. A multi-vendor flow manager controls simulation, synthesis and implementation for all devices from Actel[R], Altera[R], Lattice[R], Quicklogic[R], Xilinx[R] and other FPGA vendors. A co-simulation interface to MATLAB[R] and Simulink[R] facilitates designs with DSP. HDL language support: VHDL, Verilog[R], EDIF, SystemC and SystemVerilog. Operating system support: Windows[R] XP and Vista 32/64 bit support.

Availability

Active-HDL is available in three Product Configurations - Designer Edition (DE), Plus Edition (PE) and Expert Edition (EE). The software is available in floating or node-locked configurations for the Windows operating system. Active-HDL 8.1 is available today and is sold directly from Aldec and its authorized worldwide distributors. Download a FREE evaluation copy of Active-HDL 8.1 today.

About Aldec

Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. www.aldec.com.

Active-HDL and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.