Aldec Accelerates Verification of Altera's Nios Microprocessor-Based Designs.Business Editors/High-Tech Writers HENDERSON, Nev.--(BUSINESS WIRE)--May 3, 2004 CoVer(TM) speeds the verification of embedded systems Embedded systems Computer systems that cannot be programmed by the user because they are preprogrammed for a specific task and are buried within the equipment they serve. , providing faster time to prototype for SoCs using Altera's Nios(R) soft processor core Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices, announced today that its co-verification product, CoVer, now provides complete support for the hardware/software co-verification of Altera's Nios(R) processor. Nios customers can utilize this system for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; acceleration of the processor, in addition to having complete debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. capabilities and running software applications at MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. speed. By combining Aldec's proven HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. design entry and verification software, Active-HDL(TM), with its new CoVer technology, both hardware and software teams are able to work in parallel on the same configuration of the design from day one. Complete debugging visibility is available to both teams at all times and throughout the entire verification process. "We are pleased to be working closely with Altera to support their very popular Nios processor. We have seen a great amount of customer demand for easy-to-use, yet powerful, hardware/software verification tools for the Nios processor, and we can now support those customers with our CoVer product," said David Rinehart, director of marketing at Aldec. "CoVer for the Nios processor provides engineers designing embedded systems the necessary tools to take the successful step into the SoC world." "CoVer provides an innovative solution to hardware accelerate verified HDL code such as Altera's Nios processor while maintaining a simulation environment for new or unproven unproven Dubious, nonscientific, not proven, quack, questionable, unscientific adjective Relating to that which has not been validated by reproducible experiments or other scientific methods for determining effect or efficacy code. This ability will shorten the entire verification process," stated Joe Hanson, director of marketing system-level development tools, Altera Corporation. Concurrent Design Verification Programming Nios and all proven peripherals into CoVer hardware, (based on the Nios optimized Stratix(R) device EP-1S25), and leaving new or unproven RTL code in Active-HDL, makes concurrent design verification by both the hardware and software teams possible. This means that verification can be done very early in the design process allowing a "quicker time to prototype" for final timing verification. Import from SOPC SOPC System on a Programmable Chip SOPC Special Operations Preparation Course SOPC Second-Order Power Control SOPC Shuttle Operations and Planning Center SOPC 1-Stearoyl-2-Oleoyl-Sn-Glycero-3-Phosphatidylcholine SOPC Shaastra Online Programming Contest Builder The design team will have the ability to set the parameters of their design, including megafunctions and cores, and then import the design directly into CoVer from Altera's SOPC Builder software. This streamlines the movement from the design environment to the SoC verification platform based on well-known and proven tools. CoVer integrates Altera's Quartus(R) II design software and SOPC Builder with Aldec's Active-HDL simulator to move the Nios-based design into a fully capable software/hardware simulation environment at a very early stage of the system development. About CoVer CoVer is an easy to use platform for the verification and development of SoCs using softcore microprocessors. The CoVer platform combines a full set of tools for developing, compiling, co-simulating and debugging Nios-based systems. It provides for easier and faster modification and verification of both hardware and software parts of the system. CoVer also helps to eliminate all functional bugs and makes silicon prototyping much faster and simpler. By providing an integrated development environment See IDE. integrated development environment - interactive development environment , CoVer allows the entire design team to begin work at the same time and easily share results of their work. The use of the hardware board for acceleration of simulation provides more efficient use of available resources and reduces development time. By placing the Nios microprocessor core on the board, and keeping descriptions of the system peripherals in the HDL simulation environment, a higher level of acceleration is possible. Connection of the system level debugger Software that helps a programmer debug a program by stopping at certain breakpoints and displaying various programming elements. The programmer can step through source code statements one at a time while the corresponding machine instructions are being executed. to the board co-verifying the system with the simulator allows for simultaneous debugging of both system peripherals (HDL code) and system software. Full visibility is preserved in both cases, which usually is not possible in other solutions. The hardware board used by CoVer uses an Altera Stratix chip, is equipped with up to 256MB of memory and can work with clock speeds up to 66MHz. For more information about CoVer, please visit: http://www.aldec.com/ActiveHDL/Cover/. Pricing and Availability Pricing in the U.S. for the Altera version of Active-HDL begins at $3,995. The product supports the Windows platform. U.S. pricing for Aldec's CoVer begins at $10,000. Both products are shipping and are sold directly by Aldec in the U.S. and by authorized au·thor·ize tr.v. au·thor·ized, au·thor·iz·ing, au·thor·iz·es 1. To grant authority or power to. 2. To give permission for; sanction: distributors internationally. About Aldec, Inc. Aldec, Inc., a 20-year EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). , Linux, and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com. Active-HDL and CoVer are trademarks of Aldec, Inc. Nios, Stratix, Quartus and SOPC Builder are registered trademarks of Altera Corporation. All other trademarks or registered trademarks are property of their respective owners. |
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