Aldec's Design Flow Manager Customized for QuickLogic Devices; Provides Users With a Powerful Development Platform for Managing QuickLogic Designs.Business Editors/High-Tech Writers HENDERSON, Nev.--(BUSINESS WIRE)--Dec. 10, 2001 Aldec, Inc., a leading supplier of HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. design entry and verification software for application specific integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. (ASICs) and field programmable gate arrays, in conjunction with QuickLogic Corporation, the pioneer of ESPs (Embedded Standard Products), announced today complete support for all QuickLogic devices through Active-HDL's completely automated Design Flow Manager. Active-HDL's new Design Flow Manager supports all densities of QuickLogic devices and provides all the necessary precompiled libraries, which can be invoked during the design process. Active-HDL's Design Flow Manager allows system designers to target QuickLogic devices and includes all design components specific to QuickLogic in the process. Active-HDL comes pre-installed with all of QuickLogic's libraries so that they can be easily accessed immediately in the design cycle. Active-HDL offers full integration with QuickLogic's high-density designs, including the industry leading pASIC(R) FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. and ESP (1) (Enhanced Service Provider) An organization that adds value to basic telephone service by offering such features as call-forwarding, call-detailing and protocol conversion. device families. All aspects of implementation can be set from directly in the Active-HDL environment. Once the user chooses which family of chips he/she will be designing, the corresponding devices are automatically listed for selection. Aldec and QuickLogic are continuing to work in conjunction to ensure that QuickLogic designers' needs are met with the latest technologies in Active-HDL. QuickLogic's commitment to producing devices that support the highest-density FPGA designs prompted the alliance in order to provide system designers with the most advanced tools so that they could produce devices in the shortest time possible with the highest quality results. "QuickLogic is continually engineering new devices that will support the design requirements for all FPGA designers. QuickLogic continues to provide designers with high performance devices, and Active-HDL will continue to have the latest in QuickLogic device support," stated Megan Moran, Product Marketing Manager for Active-HDL. "We are pleased that Aldec is expanding their support for QuickLogic's ESPs and FPGAs in Active-HDL," said Mike Holmlund, product-marketing manager. "The result gives users a powerful development platform for managing their QuickLogic designs." Active-HDL's Design Flow Manager is uniquely configured to support synthesis and implementation tools from a single environment; designers can specify the specific device support that they need for each QuickLogic design. Availability Both Aldec and QuickLogic are currently offering the Active-HDL environment with QuickLogic support. The product is available as either a floating or node-lock license and includes Aldec's HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram A chart that contains squares and rectangles connected with arrows to depict hardware and software interconnections. For program flow charts, information system flow charts, circuit diagrams and communications networks, more elaborate graphical representations are usually used. & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com. About Aldec Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designers for more than 16 years. During this time, Aldec has signed several OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and agreements with IC vendors, such as Xilinx, Inc. (Nasdaq:XLNX) and Cypress Semiconductor Cypress Semiconductor is a semiconductor design and manufacturing company. It began operations in 1982 and listed publicly in 1986. Two years later, the company shifted over to the New York Stock Exchange under the symbol, (NYSE: CY). Corp. (NYSE NYSE See: New York Stock Exchange :CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL Abel, son of Adam and Eve, in the Bible Abel, in the Bible, son of Adam and Eve, a shepherd, killed by his older brother, Cain; in the Gospel of St. Matthew, mentioned as the first martyr. ). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com. About QuickLogic QuickLogic Corporation (Nasdaq:QUIK) introduced the Embedded Standard Product (ESP) architecture in 1998, creating a new class of semiconductor devices that combines the guaranteed performance and lower cost of standard products with the flexibility and time-to-market benefits of programmable logic. Since then, QuickLogic has developed more than 100 ESP solutions for OEMs in such markets as telecommunications and data communications; video/audio, graphics and imaging; instrumentation and test; high-performance computing; and military systems. For more information on the company and its products, please go to www.quicklogic.com. Note to Editors: Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners |
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