Agere Systems Uses Synopsys' Galaxy Design Platform to Tape Out Network Processor; Astro, Jupiter, Star-RCXT, and Physical Compiler Used to Tape Out Single Chip Network Processor.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 10, 2003 Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ), the world leader in semiconductor design software, today announced that Agere Systems Agere Systems Inc. was an integrated circuit components company based in Allentown, Pennsylvania, in the Lehigh Valley region of Pennsylvania, in the United States. Effective April 2, 2007, it was merged into LSI Corporation. (NYSE NYSE See: New York Stock Exchange :AGR AGR advanced gas-cooled reactor .A, AGR.B) used Synopsys' Galaxy(TM) Design Platform, employing Physical Compiler(R) physical synthesis, Astro(TM) physical design, Star-RCXT(TM) parasitic extraction, and Jupiter(TM) design planning solutions to tape out the 5G APP550 network processor in a 0.13-micron process. "Agere needed a predictable, proven design tool with advanced timing closure support for our network processor," said Bill Burroughs, technical manager within the Multiservice Networking division of Agere Systems. "By using the physical implementation tools in the Galaxy Design Platform, we met our performance target with a significant improvement in the timing-closure interval. In addition, Synopsys gave us excellent support during the design process." Agere's ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. design flow is built around Physical Compiler for achieving rapid timing closure from a register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) description to placed gates. Agere engineers used Physical Compiler's synthesis and placement together to obtain a timing-clean result in a short and predictable time. The APP550 network processor was designed using Agere's systems-on-chip (SoC) design flow, which is built around Astro for physical implementation. The tight integration between Physical Compiler and Astro's signal integrity-aware routing allowed Agere to complete the network processor on-schedule and produce parts working to specification. Several first tier global computing and communications OEMs have already chosen the APP550 for their next-generation Multiservice Networking equipment. The Agere APP500 family of products are highly integrated network A network that supports both data and voice and/or different networking protocols. See converged network and new public network. processors that have robust classification, AAL (ATM Adaption Layer) The part of the ATM protocol that breaks up application packets into 48-byte payloads which become ATM cells when the 5-byte headers are attached. The AAL resides between the higher layer transport protocols and the ATM layer. 5 segmentation and reassembly segmentation and reassembly - segmentation (SAR (Segmentation And Reassembly) The protocol that converts data to cells for transmission over an ATM network. It is the lower part of the ATM Adaption Layer (AAL), which is responsible for the entire operation. See AAL. SAR - segmentation and reassembly ), integrated world-class traffic management for multiservice applications, and on-chip Ethernet MACs. "Agere's design success with its network processor and ASICs demonstrates why the Galaxy Design Platform is at the heart of physical design for today's highly sophisticated designs," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "By providing common libraries, delay calculation and constraints with consistent timing, the Galaxy Design Platform provides fast and predictable turn-around time from design-to-results." About Galaxy Design Platform The Galaxy(TM) Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced semiconductor design. Anchored by Synopsys' industry-leading semiconductor implementation tools and the open Milkyway(TM) database, the Galaxy Design Platform incorporates consistent timing, signal integrity (SI) analysis, common libraries, delay calculation, and constraints from RTL all the way to silicon. The Galaxy Design Platform helps reduce design time, decreases integration costs and minimizes the risks inherent in advanced, complex semiconductor design. About Synopsys Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) software for semiconductor design. The Company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, Calif., and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/. Synopsys and Physical Compiler are registered trademarks of Synopsys, Inc. Astro, Galaxy, Jupiter, Milkyway, and Star-RCXT are trademarks of Synopsys, Inc. All other products mentioned in this release are the intellectual property of their respective owners. |
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