Agere Systems Tapes Out 11 Million Gate System-on-Chip Using Synopsys' Astro Physical Design Solution; Astro Speeds Design Closure for Versatile SONET/SDH Framer Chip.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Dec. 17, 2002 Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ), the technology leader for complex integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for (IC) design, today announced that Agere Systems, a premier provider of communication ICs, has taped out Agere's newest SONET/SDH framer system-on-chip (SoC) using Synopsys' Astro(TM) physical implementation solution. The Agere MARS Universal framer IC is the industry's most integrated, full-featured and versatile framer for multi-service metro and access networks - scalable from rates of 155 megabits per second (unit) megabits per second - (Mbps, Mb/s) Millions of bits per second. A unit of data rate. 1 Mb/s = 1,000,000 bits per second (not 1,048,576). E.g. Ethernet can carry 10 Mbps. to 10 gigabits per second. The chip is comprised of 11 million gates, multiple high-speed interfaces and several hundred clock domains with a system clock speed of 155 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. . The design was implemented in Agere's leading-edge 140 nanometer silicon process. Astro, a cornerstone product in Synopsys' complete RTL-to-GDSII solution, played a critical role in the completion of the chip by providing fast, highly efficient placement, routing and advanced physical optimizations. In addition, Astro is part of Agere's standard ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. SoC design flow. "Astro was vital to achieving tape out for this complex design on a tight schedule," said Jim Stefany, development director of Optical Networking Integrated Circuits at Agere. "Astro provided an excellent mix of usability and advanced capabilities, including comprehensive crosstalk prevention and correction, enabling us to efficiently close the design with correct timing, signal integrity and process rules." For this design, Agere Systems benefited from the full scope of the complete Synopsys RTL-to-GDSII solution - the industry's most complete solution with best-in-class technology for each design phase. Agere's design flow included Synopsys' Design Compiler(TM) family for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; synthesis, PrimeTime(R) for full-chip static timing analysis, Astro for physical implementation, Star-RCXT(TM) for extraction and Hercules(TM) for physical verification Physical verification A procedure auditors use to ensure that inventory recorded in the book is correct by actually checking out the physical inventory. . This familiar, trusted and production-proven design tool environment was central to achieving high productivity for Agere. "In today's environment, our customers' focus is increasingly turning to productivity where design turnaround time (1) In batch processing, the time it takes to receive finished reports after submission of documents or files for processing. In an online environment, turnaround time is the same as response time. is at a premium," said Sanjiv Kaul, senior vice president of Corporate Applications and Marketing at Synopsys. "Agere's SoC tapeout is a great example of Astro's streamlined, easy-to-use, highly productive environment that meets designer needs for fast turnaround." Astro is the most advanced physical implementation solution for designs at 130 nanometer and below. Astro extends the foundation of Apollo(TM), Synopsys' 180 nanometer place and route solution. This common design environment, user interface and Milkyway(TM) database access, makes it easy for Apollo users to migrate to Astro for better performance, higher productivity, built-in signal integrity and advance process rule support. Today, Astro is in use at nine of the world's top 10 semiconductor companies. About Synopsys Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services support services Psychology Non-health care-related ancillary services–eg, transportation, financial aid, support groups, homemaker services, respite services, and other services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com/. Synopsys and PrimeTime are registered trademarks of Synopsys, Inc., and Astro, Design Compiler, Physical Compiler, Milkyway, Hercules and Star-RCXT are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. |
|
||||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion