Agere Selects LogicVision's Embedded Test Technology for Silicon Debug and Manufacturing Test; Corporate-Wide Agreement Expands from Design to Manufacturing.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--June 4, 2002

LogicVision, Inc., (Nasdaq:LGVN), a leading provider of embedded test for integrated circuits, today announced Agere Systems, Inc. (NYSE:AGR.A), the world leader in communications components, has licensed LogicVision's Embedded Test 4.0 corporate-wide adoption for silicon design, debug and manufacturing test. Under the agreement, Agere will use LogicVision's Embedded Test 4.0 for its hierarchical test design, debug and seamless integrated manufacturing test infrastructure. LogicVision's embedded test solution allows integrated circuit designers to embed test functionality into a semiconductor design that can be used during semiconductor debug production and throughout the useful life of the chip.

"As Agere develops and manufactures complex, system-level application-specific integrated circuits incorporating millions of gates, it is crucial to obtain chip testing technologies that improve cost, quality, and reliability metrics," said Don Friedberg, director of Design Methodologies with Agere Systems, Inc. "Integrating LogicVision's Embedded Test 4.0 into Agere's highly integrated, broad portfolio of ASIC designs will enable Agere to fully test these devices and meet accelerated product development goals. When we test one of our ASIC chips, we want to make sure we can find virtually every fault in the chip. LogicVision's technology is great at meeting that objective and, in turn, helping us meet our ASIC customers' demanding time-to-market goals."

"This partnership with Agere reflects LogicVision's on-going success at further penetrating its own customer base, migrating from design to manufacturing," said Vinod Agarwal, president and CEO of LogicVision. "LogicVision offers a seamless solution for design to debug to manufacturing, which can lead to significant savings on time-to-market, reduction of capital costs, better fault coverage, and higher levels of diagnostics and quality."

As part of the multi-year agreement, Agere will deploy Embedded Test 4.0 to its design groups, delivering time-to-market value by reducing design-for-test implementation and verification time. Agere expects benefits from LogicVision's Embedded Test -- IC debug product feature in its current manufacturing test environment. Through the use of LogicVision's vector-less transfer of test data, Agere can use the tester-independent interactive user interface that enables real-time hierarchical diagnostics for logic, memory and phase lock loops. This significantly reduces silicon debug and diagnostics time, and helps manage capital expenses by extending existing tester life or enabling the use of lower-cost testers.

"This represents a strong acceptance and validation of our technology. We look forward to a continued successful relationship with Agere," said Agarwal.

About LogicVision Inc.

LogicVision (Nasdaq:LGVN) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's Embedded Test Solution(TM) allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

Forward Looking Statements:

Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected benefits of LogicVision's Embedded Test technology throughout the design, debug and manufacturing stages, including reduced debug and diagnostics time, time-to-market savings, reduced capital costs and higher levels of diagnostics and quality are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risk and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competitive products and technological advances, and other risks detailed in LogicVision's Form 10-Q for the quarter ended March 31, 2002 and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

LogicVision, Embedded Test, LogicVision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.

ACRONYMS AND DEFINITIONS:

ATE:     Automatic Test Equipment
ATPG:    Automatic Test Pattern Generation
BIST:    Built-in-Self-Test
DFT:     Design-for-Test
EDA:     Electronic Design Automation
GDSII:   An industry format describing the physical structure of the
          chip design and used to create mask tooling
          for chip manufacturing.
GUI:     Graphics User Interface
HDL:     Hardware Description Language -- Describes the architecture
          and behavior of discrete electronic systems.
IC:      Integrated Circuit
RTL:     Register Transfer-Level -- A chip design language format --
          technology independent that can be Verilog or VHDL.
Verilog: A hardware description language used to design and document
          electronic systems.
VHDL:    VHSIC (Very High-Speed Integrated Circuit) HDL
IP:      Intellectual Property
SoC:     System-on-chip