Adaptec Strengthens Verification Flow Using Tharas Systems' Hammer Hardware Accelerator.Business Editors and High Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Oct. 9, 2002 Tharas Systems, Inc., a provider of high-performance, hardware-assisted design verification solutions, announced today that Adaptec, Inc. has incorporated the Hammer(TM) hardware accelerator into its verification flow. "While designing complex integrated circuits, verifying functional accuracy is a strenuous task. By adopting the Hammer hardware accelerator, we have been able to reduce our simulation cycles significantly," says Anil Kapatkar, director of engineering for Adaptec's Storage Networking Group. "We are pleased to have Adaptec as our customer. This is a testament to the robustness of our recently announced Hammer 32M offering. With its 128-way parallel processor technology, Hammer offers leading capacity, compile times, run times, debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. features, ease-of-use, and scalability," notes Rahm Shastry, senior vice president of Marketing and Sales for Tharas Systems. Tharas Systems' Hammer provides a Verilog simulation platform that enables accelerated compile and run times, while delivering ease of use and debug features comparable to that of software simulators. Hammer compiles 10 Million RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; gate-equivalent in as little as one hour vs. up to eight hours per Million RTL gate-equivalent for FPGA-based systems. Run times range from 10 to 1,000 times faster than the fastest software HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug - a significant improvement over competing FPGA-based systems during debug. Hammer works with existing RTL and gate-level verification environments. As a result, designers can continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :SNPS SNPS Space Nuclear Power System ) and Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ). Hammer supports design sizes of up to 128 Million Gate-equivalent RTL code, and 16 Gigabyte in hardware. Hammer pricing ranges from US$115,000 to US$1,980,000. About Tharas Systems Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer(TM) offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/. For more specific product information, email info@tharas.com or call 1-408-855-3200 Hammer(TM) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
|
||||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion